diff options
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_engine_regs.h | 12 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_gt.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_hw_engine.c | 35 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_mocs.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_mocs.h | 1 |
5 files changed, 59 insertions, 2 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h index f6b3b99a562a..717d560626ce 100644 --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h @@ -44,6 +44,18 @@ #define RING_EIR(base) XE_REG((base) + 0xb0) #define RING_EMR(base) XE_REG((base) + 0xb4) #define RING_ESR(base) XE_REG((base) + 0xb8) + +#define RING_CMD_CCTL(base) XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED) +/* + * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. + * The lsb of each can be considered a separate enabling bit for encryption. + * 6:0 == default MOCS value for reads => 6:1 == table index for reads. + * 13:7 == default MOCS value for writes => 13:8 == table index for writes. + * 15:14 == Reserved => 31:30 are set to 0. + */ +#define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 8) +#define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 1) + #define RING_BBADDR(base) XE_REG((base) + 0x140) #define RING_BBADDR_UDW(base) XE_REG((base) + 0x168) #define RING_EXECLIST_STATUS_LO(base) XE_REG((base) + 0x234) diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index 0d4664e344da..603bb3ae3e37 100644 --- a/drivers/gpu/drm/xe/xe_gt.c +++ b/drivers/gpu/drm/xe/xe_gt.c @@ -390,6 +390,8 @@ static int gt_fw_domain_init(struct xe_gt *gt) /* Rerun MCR init as we now have hw engine list */ xe_gt_mcr_init(gt); + xe_mocs_init_early(gt); + err = xe_hw_engines_init_early(gt); if (err) goto err_force_wake; diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index 795302bcd3ae..04ec276cfcf5 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -21,6 +21,7 @@ #include "xe_macros.h" #include "xe_mmio.h" #include "xe_reg_sr.h" +#include "xe_rtp.h" #include "xe_sched_job.h" #include "xe_wa.h" @@ -267,6 +268,39 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe) hw_engine_mmio_read32(hwe, RING_MI_MODE(0).reg); } +static void +hw_engine_setup_default_state(struct xe_hw_engine *hwe) +{ + struct xe_gt *gt = hwe->gt; + const u8 mocs_write_idx = gt->mocs.uc_index; + /* TODO: missing handling of HAS_L3_CCS_READ platforms */ + const u8 mocs_read_idx = gt->mocs.uc_index; + u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) | + REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx); + const struct xe_rtp_entry engine_was[] = { + /* + * RING_CMD_CCTL specifies the default MOCS entry that will be + * used by the command streamer when executing commands that + * don't have a way to explicitly specify a MOCS setting. + * The default should usually reference whichever MOCS entry + * corresponds to uncached behavior, although use of a WB cached + * entry is recommended by the spec in certain circumstances on + * specific platforms. + */ + { XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED)), + XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0), + CMD_CCTL_WRITE_OVERRIDE_MASK | + CMD_CCTL_READ_OVERRIDE_MASK, + ring_cmd_cctl_val, + XE_RTP_ACTION_FLAG(ENGINE_BASE))) + }, + {} + }; + + xe_rtp_process(engine_was, &hwe->reg_sr, gt, hwe); +} + static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe, enum xe_hw_engine_id id) { @@ -293,6 +327,7 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe, xe_reg_sr_init(&hwe->reg_sr, hwe->name, gt_to_xe(gt)); xe_wa_process_engine(hwe); + hw_engine_setup_default_state(hwe); xe_reg_sr_init(&hwe->reg_whitelist, hwe->name, gt_to_xe(gt)); xe_reg_whitelist_process_engine(hwe); diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c index f2ceecd536ed..0d07811a573f 100644 --- a/drivers/gpu/drm/xe/xe_mocs.c +++ b/drivers/gpu/drm/xe/xe_mocs.c @@ -518,6 +518,15 @@ static void init_l3cc_table(struct xe_gt *gt, } } +void xe_mocs_init_early(struct xe_gt *gt) +{ + struct xe_mocs_info table; + + get_mocs_settings(gt->xe, &table); + gt->mocs.uc_index = table.uc_index; + gt->mocs.wb_index = table.wb_index; +} + void xe_mocs_init(struct xe_gt *gt) { struct xe_mocs_info table; @@ -528,8 +537,6 @@ void xe_mocs_init(struct xe_gt *gt) */ flags = get_mocs_settings(gt->xe, &table); mocs_dbg(>->xe->drm, "flag:0x%x\n", flags); - gt->mocs.uc_index = table.uc_index; - gt->mocs.wb_index = table.wb_index; if (flags & HAS_GLOBAL_MOCS) __init_mocs_table(gt, &table, GLOBAL_MOCS(0).reg); diff --git a/drivers/gpu/drm/xe/xe_mocs.h b/drivers/gpu/drm/xe/xe_mocs.h index 63500a1d6660..25f7b35a76da 100644 --- a/drivers/gpu/drm/xe/xe_mocs.h +++ b/drivers/gpu/drm/xe/xe_mocs.h @@ -11,6 +11,7 @@ struct xe_engine; struct xe_gt; +void xe_mocs_init_early(struct xe_gt *gt); void xe_mocs_init(struct xe_gt *gt); /** |