diff options
| -rw-r--r-- | drivers/media/i2c/imx258.c | 109 |
1 files changed, 71 insertions, 38 deletions
diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c index 4eb5f2eba491..32267d36b8f3 100644 --- a/drivers/media/i2c/imx258.c +++ b/drivers/media/i2c/imx258.c @@ -99,6 +99,11 @@ struct imx258_reg_list { const struct imx258_reg *regs; }; +struct imx258_link_cfg { + unsigned int lf_to_pix_rate_factor; + struct imx258_reg_list reg_list; +}; + enum { IMX258_2_LANE_MODE, IMX258_4_LANE_MODE, @@ -109,8 +114,8 @@ enum { struct imx258_link_freq_config { u32 pixels_per_line; - /* PLL registers for this link frequency */ - struct imx258_reg_list reg_list[IMX258_LANE_CONFIGS]; + /* Configuration for this link frequency / num lanes selection */ + struct imx258_link_cfg link_cfg[IMX258_LANE_CONFIGS]; }; /* Mode : resolution and related config&values */ @@ -273,7 +278,7 @@ static const struct imx258_reg mipi_640mbps_19_2mhz_4l[] = { static const struct imx258_reg mipi_642mbps_24mhz_2l[] = { { 0x0136, 0x18 }, { 0x0137, 0x00 }, - { 0x0301, 0x0A }, + { 0x0301, 0x05 }, { 0x0303, 0x02 }, { 0x0305, 0x04 }, { 0x0306, 0x00 }, @@ -479,14 +484,22 @@ enum { }; /* - * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample - * data rate => double data rate; - * number of lanes => (configurable 2 or 4); - * bits per pixel => 10 + * Pixel rate does not necessarily relate to link frequency on this sensor as + * there is a FIFO between the pixel array pipeline and the MIPI serializer. + * The recommendation from Sony is that the pixel array is always run with a + * line length of 5352 pixels, which means that there is a large amount of + * blanking time for the 1048x780 mode. There is no need to replicate this + * blanking on the CSI2 bus, and the configuration of register 0x0301 allows the + * divider to be altered. + * + * The actual factor between link frequency and pixel rate is in the + * imx258_link_cfg, so use this to convert between the two. + * bits per pixel being 10, and D-PHY being DDR is assumed by this function, so + * the value is only the combination of number of lanes and pixel clock divider. */ -static u64 link_freq_to_pixel_rate(u64 f, unsigned int nlanes) +static u64 link_freq_to_pixel_rate(u64 f, const struct imx258_link_cfg *link_cfg) { - f *= 2 * nlanes; + f *= 2 * link_cfg->lf_to_pix_rate_factor; do_div(f, 10); return f; @@ -504,31 +517,33 @@ static const s64 link_freq_menu_items_24[] = { 321000000ULL, }; +#define REGS(_list) { .num_of_regs = ARRAY_SIZE(_list), .regs = _list, } + /* Link frequency configs */ static const struct imx258_link_freq_config link_freq_configs_19_2[] = { [IMX258_LINK_FREQ_1267MBPS] = { .pixels_per_line = IMX258_PPL_DEFAULT, - .reg_list = { + .link_cfg = { [IMX258_2_LANE_MODE] = { - .num_of_regs = ARRAY_SIZE(mipi_1267mbps_19_2mhz_2l), - .regs = mipi_1267mbps_19_2mhz_2l, + .lf_to_pix_rate_factor = 2 * 2, + .reg_list = REGS(mipi_1267mbps_19_2mhz_2l), }, [IMX258_4_LANE_MODE] = { - .num_of_regs = ARRAY_SIZE(mipi_1267mbps_19_2mhz_4l), - .regs = mipi_1267mbps_19_2mhz_4l, + .lf_to_pix_rate_factor = 4, + .reg_list = REGS(mipi_1267mbps_19_2mhz_4l), }, } }, [IMX258_LINK_FREQ_640MBPS] = { .pixels_per_line = IMX258_PPL_DEFAULT, - .reg_list = { + .link_cfg = { [IMX258_2_LANE_MODE] = { - .num_of_regs = ARRAY_SIZE(mipi_640mbps_19_2mhz_2l), - .regs = mipi_640mbps_19_2mhz_2l, + .lf_to_pix_rate_factor = 2, + .reg_list = REGS(mipi_640mbps_19_2mhz_2l), }, [IMX258_4_LANE_MODE] = { - .num_of_regs = ARRAY_SIZE(mipi_640mbps_19_2mhz_4l), - .regs = mipi_640mbps_19_2mhz_4l, + .lf_to_pix_rate_factor = 4, + .reg_list = REGS(mipi_640mbps_19_2mhz_4l), }, } }, @@ -537,27 +552,27 @@ static const struct imx258_link_freq_config link_freq_configs_19_2[] = { static const struct imx258_link_freq_config link_freq_configs_24[] = { [IMX258_LINK_FREQ_1267MBPS] = { .pixels_per_line = IMX258_PPL_DEFAULT, - .reg_list = { + .link_cfg = { [IMX258_2_LANE_MODE] = { - .num_of_regs = ARRAY_SIZE(mipi_1272mbps_24mhz_2l), - .regs = mipi_1272mbps_24mhz_2l, + .lf_to_pix_rate_factor = 2, + .reg_list = REGS(mipi_1272mbps_24mhz_2l), }, [IMX258_4_LANE_MODE] = { - .num_of_regs = ARRAY_SIZE(mipi_1272mbps_24mhz_4l), - .regs = mipi_1272mbps_24mhz_4l, + .lf_to_pix_rate_factor = 4, + .reg_list = REGS(mipi_1272mbps_24mhz_4l), }, } }, [IMX258_LINK_FREQ_640MBPS] = { .pixels_per_line = IMX258_PPL_DEFAULT, - .reg_list = { + .link_cfg = { [IMX258_2_LANE_MODE] = { - .num_of_regs = ARRAY_SIZE(mipi_642mbps_24mhz_2l), - .regs = mipi_642mbps_24mhz_2l, + .lf_to_pix_rate_factor = 2 * 2, + .reg_list = REGS(mipi_642mbps_24mhz_2l), }, [IMX258_4_LANE_MODE] = { - .num_of_regs = ARRAY_SIZE(mipi_642mbps_24mhz_4l), - .regs = mipi_642mbps_24mhz_4l, + .lf_to_pix_rate_factor = 4, + .reg_list = REGS(mipi_642mbps_24mhz_4l), }, } }, @@ -635,7 +650,7 @@ struct imx258 { const struct imx258_link_freq_config *link_freq_configs; const s64 *link_freq_menu_items; - unsigned int nlanes; + unsigned int lane_mode_idx; unsigned int csi2_flags; /* @@ -945,8 +960,10 @@ static int imx258_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_format *fmt) { struct imx258 *imx258 = to_imx258(sd); - const struct imx258_mode *mode; + const struct imx258_link_freq_config *link_freq_cfgs; + const struct imx258_link_cfg *link_cfg; struct v4l2_mbus_framefmt *framefmt; + const struct imx258_mode *mode; s32 vblank_def; s32 vblank_min; s64 h_blank; @@ -970,7 +987,11 @@ static int imx258_set_pad_format(struct v4l2_subdev *sd, __v4l2_ctrl_s_ctrl(imx258->link_freq, mode->link_freq_index); link_freq = imx258->link_freq_menu_items[mode->link_freq_index]; - pixel_rate = link_freq_to_pixel_rate(link_freq, imx258->nlanes); + link_freq_cfgs = + &imx258->link_freq_configs[mode->link_freq_index]; + + link_cfg = &link_freq_cfgs->link_cfg[imx258->lane_mode_idx]; + pixel_rate = link_freq_to_pixel_rate(link_freq, link_cfg); __v4l2_ctrl_modify_range(imx258->pixel_rate, pixel_rate, pixel_rate, 1, pixel_rate); /* Update limits and set FPS to default */ @@ -1068,7 +1089,8 @@ static int imx258_start_streaming(struct imx258 *imx258) /* Setup PLL */ link_freq_index = imx258->cur_mode->link_freq_index; link_freq_cfg = &imx258->link_freq_configs[link_freq_index]; - reg_list = &link_freq_cfg->reg_list[imx258->nlanes == 2 ? 0 : 1]; + + reg_list = &link_freq_cfg->link_cfg[imx258->lane_mode_idx].reg_list; ret = imx258_write_regs(imx258, reg_list->regs, reg_list->num_of_regs); if (ret) { dev_err(&client->dev, "%s failed to set plls\n", __func__); @@ -1257,9 +1279,11 @@ static const struct v4l2_subdev_internal_ops imx258_internal_ops = { static int imx258_init_controls(struct imx258 *imx258) { struct i2c_client *client = v4l2_get_subdevdata(&imx258->sd); + const struct imx258_link_freq_config *link_freq_cfgs; struct v4l2_fwnode_device_properties props; - struct v4l2_ctrl_handler *ctrl_hdlr; struct v4l2_ctrl *vflip, *hflip; + struct v4l2_ctrl_handler *ctrl_hdlr; + const struct imx258_link_cfg *link_cfg; s64 vblank_def; s64 vblank_min; s64 pixel_rate; @@ -1293,8 +1317,11 @@ static int imx258_init_controls(struct imx258 *imx258) if (vflip) vflip->flags |= V4L2_CTRL_FLAG_READ_ONLY; + link_freq_cfgs = &imx258->link_freq_configs[0]; + link_cfg = link_freq_cfgs[imx258->lane_mode_idx].link_cfg; pixel_rate = link_freq_to_pixel_rate(imx258->link_freq_menu_items[0], - imx258->nlanes); + link_cfg); + /* By default, PIXEL_RATE is read only */ imx258->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx258_ctrl_ops, V4L2_CID_PIXEL_RATE, @@ -1448,10 +1475,16 @@ static int imx258_probe(struct i2c_client *client) } /* Get number of data lanes */ - imx258->nlanes = ep.bus.mipi_csi2.num_data_lanes; - if (imx258->nlanes != 2 && imx258->nlanes != 4) { + switch (ep.bus.mipi_csi2.num_data_lanes) { + case 2: + imx258->lane_mode_idx = IMX258_2_LANE_MODE; + break; + case 4: + imx258->lane_mode_idx = IMX258_4_LANE_MODE; + break; + default: dev_err(&client->dev, "Invalid data lanes: %u\n", - imx258->nlanes); + ep.bus.mipi_csi2.num_data_lanes); ret = -EINVAL; goto error_endpoint_free; } |