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| author | Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> | 2022-09-19 13:53:47 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-09-19 18:11:44 +0100 |
| commit | 9ccbc2e12e01b39b804774c3207d2474dd992d95 (patch) | |
| tree | 86adbeb6e624448e38193c8f694a4c8dd684a496 /sound/soc/sof/intel/tgl.c | |
| parent | d3cfe45f5f59f33137ce2a009c475f34dfd7f830 (diff) | |
| download | lwn-9ccbc2e12e01b39b804774c3207d2474dd992d95.tar.gz lwn-9ccbc2e12e01b39b804774c3207d2474dd992d95.zip | |
ASoC: SOF: Intel: hda: refine SSP count support
The SSP count is incorrect for TGL and MTL devices, the SSP count is
limited to 3 (I2SPC parameter in the Integration HAS).
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20220919115350.43104-2-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/sof/intel/tgl.c')
| -rw-r--r-- | sound/soc/sof/intel/tgl.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sound/soc/sof/intel/tgl.c b/sound/soc/sof/intel/tgl.c index 017bf331ed5a..5135e1c7e6cf 100644 --- a/sound/soc/sof/intel/tgl.c +++ b/sound/soc/sof/intel/tgl.c @@ -123,7 +123,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = { .ipc_ctl = CNL_DSP_REG_HIPCCTL, .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, .rom_init_timeout = 300, - .ssp_count = ICL_SSP_COUNT, + .ssp_count = TGL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, .sdw_shim_base = SDW_SHIM_BASE, .sdw_alh_base = SDW_ALH_BASE, @@ -146,7 +146,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = { .ipc_ctl = CNL_DSP_REG_HIPCCTL, .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, .rom_init_timeout = 300, - .ssp_count = ICL_SSP_COUNT, + .ssp_count = TGL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, .sdw_shim_base = SDW_SHIM_BASE, .sdw_alh_base = SDW_ALH_BASE, @@ -169,7 +169,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = { .ipc_ctl = CNL_DSP_REG_HIPCCTL, .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, .rom_init_timeout = 300, - .ssp_count = ICL_SSP_COUNT, + .ssp_count = TGL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, .sdw_shim_base = SDW_SHIM_BASE, .sdw_alh_base = SDW_ALH_BASE, @@ -192,7 +192,7 @@ const struct sof_intel_dsp_desc adls_chip_info = { .ipc_ctl = CNL_DSP_REG_HIPCCTL, .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, .rom_init_timeout = 300, - .ssp_count = ICL_SSP_COUNT, + .ssp_count = TGL_SSP_COUNT, .ssp_base_offset = CNL_SSP_BASE_OFFSET, .sdw_shim_base = SDW_SHIM_BASE, .sdw_alh_base = SDW_ALH_BASE, |