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| author | Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> | 2022-10-13 10:38:31 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-10-13 13:01:34 +0100 |
| commit | c9a3545b1d771fb7b06a487796c40288c02c41c5 (patch) | |
| tree | 23f89c9f7d7798376414d4411cd0d38498922cdc /sound/soc/qcom/lpass-cpu.c | |
| parent | ee1aa2ae3eaa96e70229fa61deee87ef4528ffdf (diff) | |
| download | lwn-c9a3545b1d771fb7b06a487796c40288c02c41c5.tar.gz lwn-c9a3545b1d771fb7b06a487796c40288c02c41c5.zip | |
ASoC: qcom: lpass-cpu: mark HDMI TX registers as volatile
Update HDMI volatile registers list as DMA, Channel Selection registers,
vbit control registers are being reflected by hardware DP port
disconnection.
This update is required to fix no display and no sound issue observed
after reconnecting TAMA/SANWA DP cables.
Once DP cable is unplugged, DMA control registers are being reset by
hardware, however at second plugin, new dma control values does not
updated to the dma hardware registers since new register value and
cached values at the time of first plugin are same.
Fixes: 7cb37b7bd0d3 ("ASoC: qcom: Add support for lpass hdmi driver")
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reported-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Link: https://lore.kernel.org/r/1665637711-13300-1-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/qcom/lpass-cpu.c')
| -rw-r--r-- | sound/soc/qcom/lpass-cpu.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index 8a56f38dc7e8..99a3b4428591 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -782,10 +782,18 @@ static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg) return true; if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) return true; + if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) + return true; for (i = 0; i < v->hdmi_rdma_channels; ++i) { if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) return true; + if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) + return true; + if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) + return true; + if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) + return true; } return false; } |