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| author | Syed Saba Kareem <Syed.SabaKareem@amd.com> | 2023-10-21 20:20:43 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-10-25 17:21:44 +0100 |
| commit | 40f74d5f09d7c068bd7a980dc06a688dc8d2b3e3 (patch) | |
| tree | ac8deac00dcd618b39b5ddee6c9a837b3d837c56 /sound/soc/amd/acp/amd.h | |
| parent | 33d120a49b970acbe465041d7b71e0cd6a1d1de0 (diff) | |
| download | lwn-40f74d5f09d7c068bd7a980dc06a688dc8d2b3e3.tar.gz lwn-40f74d5f09d7c068bd7a980dc06a688dc8d2b3e3.zip | |
ASoC: amd: acp: refactor acp i2s clock generation code
Refactor acp i2s LRCLK,BCLK generation code and move to commnon file.
Signed-off-by: Syed Saba Kareem <Syed.SabaKareem@amd.com>
Link: https://lore.kernel.org/r/20231021145110.478744-2-Syed.SabaKareem@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/amd/acp/amd.h')
| -rw-r--r-- | sound/soc/amd/acp/amd.h | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/sound/soc/amd/acp/amd.h b/sound/soc/amd/acp/amd.h index 487eefa5985f..87d1e1f7d6b6 100644 --- a/sound/soc/amd/acp/amd.h +++ b/sound/soc/amd/acp/amd.h @@ -188,17 +188,6 @@ struct acp_dev_data { u32 xfer_rx_resolution[3]; }; -union acp_i2stdm_mstrclkgen { - struct { - u32 i2stdm_master_mode : 1; - u32 i2stdm_format_mode : 1; - u32 i2stdm_lrclk_div_val : 9; - u32 i2stdm_bclk_div_val : 11; - u32:10; - } bitfields, bits; - u32 u32_all; -}; - extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops; extern const struct snd_soc_dai_ops acp_dmic_dai_ops; @@ -276,32 +265,4 @@ static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int POINTER_RETURN_BYTES: return byte_count; } - -static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id) -{ - union acp_i2stdm_mstrclkgen mclkgen; - u32 master_reg; - - switch (dai_id) { - case I2S_SP_INSTANCE: - master_reg = ACP_I2STDM0_MSTRCLKGEN; - break; - case I2S_BT_INSTANCE: - master_reg = ACP_I2STDM1_MSTRCLKGEN; - break; - case I2S_HS_INSTANCE: - master_reg = ACP_I2STDM2_MSTRCLKGEN; - break; - default: - master_reg = ACP_I2STDM0_MSTRCLKGEN; - break; - } - - mclkgen.bits.i2stdm_master_mode = 0x1; - mclkgen.bits.i2stdm_format_mode = 0x00; - - mclkgen.bits.i2stdm_bclk_div_val = adata->bclk_div; - mclkgen.bits.i2stdm_lrclk_div_val = adata->lrclk_div; - writel(mclkgen.u32_all, adata->acp_base + master_reg); -} #endif |