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| author | Andrew Jones <andrew.jones@oss.qualcomm.com> | 2026-08-21 13:21:00 +0200 |
|---|---|---|
| committer | Joerg Roedel <joerg.roedel@amd.com> | 2026-09-24 13:19:26 +0200 |
| commit | 3069e8f3e1e9bdf007316eadae4d1777065e7b78 (patch) | |
| tree | 1170c56acf71b86d57f0619ac78b4efbf5926660 /scripts/dummy-tools/python3 | |
| parent | 93f51579e7df248780214094418f205253383cc5 (diff) | |
| download | lwn-3069e8f3e1e9bdf007316eadae4d1777065e7b78.tar.gz lwn-3069e8f3e1e9bdf007316eadae4d1777065e7b78.zip | |
iommu/riscv: Report cache coherency capability
VFIO and iommufd require IOMMU_CAP_CACHE_COHERENCY because they use
IOMMU_CACHE mappings and have no userspace cache-maintenance path.
RISC-V page tables preserve physical memory attributes for IOMMU_CACHE
mappings. Svpbmt marks mappings without IOMMU_CACHE as non-cacheable,
but preserving physical attributes cannot make a noncoherent device
path coherent.
Report the capability only for devices marked DMA coherent. This limits
userspace assignment to paths that can honor cacheable mappings.
Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'scripts/dummy-tools/python3')
0 files changed, 0 insertions, 0 deletions