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author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2016-01-26 10:58:13 +0000 |
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committer | Catalin Marinas <catalin.marinas@arm.com> | 2016-02-25 10:33:07 +0000 |
commit | e53435031a541762223b03f5e6f0ebd98bdf3501 (patch) | |
tree | 387a50a10af781873d3dc5a69e0a898e3d1a2ce7 /samples | |
parent | 13f417f3b83f78de402f1674aa9009f778d768c3 (diff) | |
download | lwn-e53435031a541762223b03f5e6f0ebd98bdf3501.tar.gz lwn-e53435031a541762223b03f5e6f0ebd98bdf3501.zip |
arm64: cpufeature: Correct feature register tables
Correct the feature bit entries for :
ID_DFR0
ID_MMFR0
to fix the default safe value for some of the bits.
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'samples')
0 files changed, 0 insertions, 0 deletions