Merge tag 'renesas-dts-for-v7.2-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v7.2 (take two)

  - Add timer (MTU3) and xSPI FLASH support for the RZ/T2H and RZ/N2H
    SoCs and their EVK boards,
  - Add PCIe support for the RZ/V2N SoC and the RZ/V2N EVK board,
  - Add support for the R-Car M3Le SoC and the Geist development board,
  - Specify ethernet PHY reset timings on various R-Car boards,
  - Add (more) serial, I2C, DMA, and sound support for the RZ/G3L SoC,
  - Add PSCI, Multifunctional Interface (MFIS), and SCMI support for the
    R-Car X5H SoC and Ironhide development board,
  - Add serial DMA support for the RZ/G2L SoC,
  - Add keyboard, I2C, Versa clock, and audio support for the RZ/G3L
    SMARC SoM and EVK boards,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v7.2-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (56 commits)
  arm64: dts: renesas: r9a08g046l48-smarc: Enable audio
  arm64: dts: renesas: rzg3l-smarc-som: Enable Versa clock generator
  arm64: dts: renesas: r9a08g046l48-smarc: Enable I2C{2,3} devices
  arm64: dts: renesas: r9a08g046l48-smarc: Add gpio keys
  arm64: dts: renesas: rzt2h-n2h-evk: Enable xSPI nodes
  arm64: dts: renesas: r9a09g087: Add xSPI nodes
  arm64: dts: renesas: r9a09g077: Add xSPI nodes
  arm64: dts: renesas: rzg3e-smarc-som: Sort GMAC pinmux entries
  arm64: dts: renesas: r8a779md: Add support for R-Car M3Le R8A779MD Geist
  arm64: dts: renesas: r9a07g044: Add DMA properties to serial nodes
  arm64: dts: renesas: r9a07g054: Add max-frequency to SDHI nodes
  arm64: dts: renesas: r9a07g044: Add max-frequency to SDHI nodes
  arm64: dts: renesas: r9a07g043: Add max-frequency to SDHI nodes
  arm64: dts: renesas: r9a08g046: Add rsci{0..3} device nodes
  arm64: dts: renesas: ironhide: Enable to use SCMI
  arm64: dts: renesas: r8a78000: Add MFIS, MFIS-SCP, and transport nodes
  arm64: dts: renesas: ironhide: Describe all reserved memory
  arm64: dts: renesas: rzt2h-n2h-evk: Configure eMMC/SDHI pins
  arm64: dts: renesas: r8a78000: Fix GIC-720AE View 1 Redistributor description
  arm64: dts: renesas: r8a78000: Add PSCI node
  ...

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

1 files changed, 28 insertions, 0 deletions

diff --git a/include/dt-bindings/soc/renesas,r8a78000-mfis.h b/include/dt-bindings/soc/renesas,r8a78000-mfis.h
new file mode 100644
index 000000000000..147a8aefc643
--- /dev/null
+++ b/include/dt-bindings/soc/renesas,r8a78000-mfis.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H
+#define _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H
+
+/*
+ * Constants for the second mbox-cell of the Renesas MFIS IP core. To be treated
+ * as bit flags which can be ORed.
+ */
+
+/*
+ * MFIS HW design before r8a78001 requires a channel to be marked as either
+ * TX or RX.
+ */
+#define MFIS_CHANNEL_TX (0 << 0)
+#define MFIS_CHANNEL_RX (1 << 0)
+
+/*
+ * MFIS variants before r8a78001 work with pairs of IICR and EICR registers.
+ * Usually, it is specified in the datasheets which of the two a specific core
+ * should use. Then, it does not need extra description in DT. For plain MFIS
+ * of r8a78000, this is selectable, though. According to the system design and
+ * the firmware in use, these channels need to be marked. This is not needed
+ * with other versions of the MFIS, not even with MFIS-SCP of r8a78000.
+ */
+#define MFIS_CHANNEL_IICR (0 << 1)
+#define MFIS_CHANNEL_EICR (1 << 1)
+
+#endif /* _DT_BINDINGS_SOC_RENESAS_R8A78000_MFIS_H */