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| author | Arvind Yadav <arvind.yadav@intel.com> | 2026-03-26 18:38:38 +0530 |
|---|---|---|
| committer | Matthew Brost <matthew.brost@intel.com> | 2026-03-26 19:59:54 -0700 |
| commit | 05c8b1cdc54036465ea457a0501a8c2f9409fce7 (patch) | |
| tree | 0e02d4928b4bb8ebb9735d65fef41091c19ae290 /include/ras | |
| parent | 4def73ec3d000a8347b2b63f4ecc5b1e3b476941 (diff) | |
| download | lwn-05c8b1cdc54036465ea457a0501a8c2f9409fce7.tar.gz lwn-05c8b1cdc54036465ea457a0501a8c2f9409fce7.zip | |
drm/xe/madvise: Accept canonical GPU addresses in xe_vm_madvise_ioctl
Userspace passes canonical (sign-extended) GPU addresses where bits 63:48
mirror bit 47. The internal GPUVM uses non-canonical form (upper bits
zeroed), so passing raw canonical addresses into GPUVM lookups causes
mismatches for addresses above 128TiB.
Strip the sign extension with xe_device_uncanonicalize_addr() at the
top of xe_vm_madvise_ioctl(). Non-canonical addresses are unaffected.
Fixes: ada7486c5668 ("drm/xe: Implement madvise ioctl for xe")
Suggested-by: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Arvind Yadav <arvind.yadav@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20260326130843.3545241-13-arvind.yadav@intel.com
Diffstat (limited to 'include/ras')
0 files changed, 0 insertions, 0 deletions