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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2026-02-13 18:10:09 +0100 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2026-02-13 18:10:09 +0100 |
| commit | 7e96d76c74175ef9747f6fc14ee567f89d72153c (patch) | |
| tree | ca62cab4867acccdf339e2b199c247b910e24a8b /include/linux/spi | |
| parent | 875382759298650c96192bf2c12e2d1e4575de92 (diff) | |
| parent | 6c7860aa28b81b7e909b8d2072ed76fa22db6eda (diff) | |
| download | lwn-7e96d76c74175ef9747f6fc14ee567f89d72153c.tar.gz lwn-7e96d76c74175ef9747f6fc14ee567f89d72153c.zip | |
Merge tag 'nand/for-7.0' into mtd/next
SPI NAND
- The major feature this release is the support for octal DTR
modes (8D-8D-8D).
- There has been as well a series of conversion to scoped for each OF
child loops.
- Support for Foresee F35SQB002G chips has been added.
Other changes are small fixes.
Diffstat (limited to 'include/linux/spi')
| -rw-r--r-- | include/linux/spi/spi-mem.h | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 82390712794c..5774e554c0f0 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -20,10 +20,10 @@ .opcode = __opcode, \ } -#define SPI_MEM_DTR_OP_CMD(__opcode, __buswidth) \ +#define SPI_MEM_DTR_OP_RPT_CMD(__opcode, __buswidth) \ { \ - .nbytes = 1, \ - .opcode = __opcode, \ + .nbytes = 2, \ + .opcode = __opcode | __opcode << 8, \ .buswidth = __buswidth, \ .dtr = true, \ } @@ -43,6 +43,22 @@ .dtr = true, \ } +#define SPI_MEM_DTR_OP_RPT_ADDR(__val, __buswidth) \ + { \ + .nbytes = 2, \ + .val = __val | __val << 8, \ + .buswidth = __buswidth, \ + .dtr = true, \ + } + +#define SPI_MEM_DTR_OP_RPT_ADDR(__val, __buswidth) \ + { \ + .nbytes = 2, \ + .val = __val | __val << 8, \ + .buswidth = __buswidth, \ + .dtr = true, \ + } + #define SPI_MEM_OP_NO_ADDR { } #define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \ |