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| author | Mark Brown <broonie@kernel.org> | 2022-09-15 10:29:01 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-09-15 10:29:01 +0100 |
| commit | 12e51866c79fe37faed276442f4b0dfd9f2dc174 (patch) | |
| tree | 8c2c85171d6eb06fbc7c4d0e06ed8be97a3448cc /include/linux/mlx5/driver.h | |
| parent | a6b0be65123e1dfbcce6653a82394f989d3372ff (diff) | |
| parent | b2d7616e13c4eb766f5e2f6568c2e746e76b7b53 (diff) | |
| download | lwn-12e51866c79fe37faed276442f4b0dfd9f2dc174.tar.gz lwn-12e51866c79fe37faed276442f4b0dfd9f2dc174.zip | |
ASoC/qcom/arm64: Qualcomm ADSP DTS and binding fixes
Merge series from Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>:
Hi,
Dependencies/merging
====================
1. The DTS patches are independent.
2. The binding patches should come together, because of context changes. Could
be one of: Qualcomm SoC, ASoC or DT tree.
Changes since v3
================
1. Patch 9-10: re-order, so first apr.yaml is corrected and then we convert to
DT schema. This makes patchset fully bisectable in expense of changing the same
lines twice.
2. Patch 11: New patch.
Changes since v2
================
1. Patch 9: rename and extend commit msg.
2. Add Rb tags.
Changes since v1
================
1. Patch 9: New patch.
2. Patch 10: Correct also sound/qcom,q6apm-dai.yaml (Rob).
2. Patch 13: New patch.
3. Add Rb/Tb tags.
Best regards,
Krzysztof
Krzysztof Kozlowski (15):
arm64: dts: qcom: sdm630: align APR services node names with dtschema
arm64: dts: qcom: sdm845: align APR services node names with dtschema
arm64: dts: qcom: sm8250: align APR services node names with dtschema
arm64: dts: qcom: msm8996: fix APR services nodes
arm64: dts: qcom: sdm845: align dai node names with dtschema
arm64: dts: qcom: msm8996: align dai node names with dtschema
arm64: dts: qcom: qrb5165-rb5: align dai node names with dtschema
arm64: dts: qcom: sm8250: use generic name for LPASS clock controller
dt-bindings: soc: qcom: apr: correct service children
ASoC: dt-bindings: qcom,q6asm: convert to dtschema
ASoC: dt-bindings: qcom,q6adm: convert to dtschema
ASoC: dt-bindings: qcom,q6dsp-lpass-ports: cleanup example
ASoC: dt-bindings: qcom,q6dsp-lpass-clocks: cleanup example
ASoC: dt-bindings: qcom,q6apm-dai: adjust indentation in example
dt-bindings: soc: qcom: apr: add missing properties
.../bindings/soc/qcom/qcom,apr.yaml | 112 ++++++++++++++++--
.../bindings/sound/qcom,q6adm-routing.yaml | 52 ++++++++
.../devicetree/bindings/sound/qcom,q6adm.txt | 39 ------
.../bindings/sound/qcom,q6apm-dai.yaml | 21 ++--
.../bindings/sound/qcom,q6asm-dais.yaml | 112 ++++++++++++++++++
.../devicetree/bindings/sound/qcom,q6asm.txt | 70 -----------
.../sound/qcom,q6dsp-lpass-clocks.yaml | 36 +++---
.../sound/qcom,q6dsp-lpass-ports.yaml | 64 +++++-----
arch/arm64/boot/dts/qcom/msm8996.dtsi | 10 +-
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 4 +-
arch/arm64/boot/dts/qcom/sdm630.dtsi | 8 +-
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +-
.../boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 2 +-
.../boot/dts/qcom/sdm845-xiaomi-polaris.dts | 4 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +-
16 files changed, 346 insertions(+), 208 deletions(-)
create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6adm-routing.yaml
delete mode 100644 Documentation/devicetree/bindings/sound/qcom,q6adm.txt
create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6asm-dais.yaml
delete mode 100644 Documentation/devicetree/bindings/sound/qcom,q6asm.txt
--
2.34.1
Diffstat (limited to 'include/linux/mlx5/driver.h')
| -rw-r--r-- | include/linux/mlx5/driver.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 7b7ce602c808..c32de987fa71 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -1280,16 +1280,17 @@ enum { MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, }; -static inline bool mlx5_is_roce_init_enabled(struct mlx5_core_dev *dev) +bool mlx5_is_roce_on(struct mlx5_core_dev *dev); + +static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev) { - struct devlink *devlink = priv_to_devlink(dev); - union devlink_param_value val; - int err; - - err = devlink_param_driverinit_value_get(devlink, - DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, - &val); - return err ? MLX5_CAP_GEN(dev, roce) : val.vbool; + if (MLX5_CAP_GEN(dev, roce_rw_supported)) + return MLX5_CAP_GEN(dev, roce); + + /* If RoCE cap is read-only in FW, get RoCE state from devlink + * in order to support RoCE enable/disable feature + */ + return mlx5_is_roce_on(dev); } #endif /* MLX5_DRIVER_H */ |
