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authorSmita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>2025-01-23 08:44:19 +0000
committerDave Jiang <dave.jiang@intel.com>2025-02-06 11:27:28 -0700
commit315c2f0b53ba2645062627443a12cea73f3dad9c (patch)
tree9cb8522771d0bdec503f9a894c37eaa3ba14b057 /include/cxl
parent61eac5f7f6439e8fe99b5fb29406acb0fd7b83c6 (diff)
downloadlwn-315c2f0b53ba2645062627443a12cea73f3dad9c.tar.gz
lwn-315c2f0b53ba2645062627443a12cea73f3dad9c.zip
acpi/ghes, cper: Recognize and cache CXL Protocol errors
Add support in GHES to detect and process CXL CPER Protocol errors, as defined in UEFI v2.10, section N.2.13. Define struct cxl_cper_prot_err_work_data to cache CXL protocol error information, including RAS capabilities and severity, for further handling. These cached CXL CPER records will later be processed by workqueues within the CXL subsystem. Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250123084421.127697-5-Smita.KoralahalliChannabasappa@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'include/cxl')
-rw-r--r--include/cxl/event.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/cxl/event.h b/include/cxl/event.h
index 7a6c14c05215..8381a07052d0 100644
--- a/include/cxl/event.h
+++ b/include/cxl/event.h
@@ -244,6 +244,12 @@ struct cxl_ras_capability_regs {
u32 header_log[16];
};
+struct cxl_cper_prot_err_work_data {
+ struct cxl_cper_sec_prot_err prot_err;
+ struct cxl_ras_capability_regs ras_cap;
+ int severity;
+};
+
#ifdef CONFIG_ACPI_APEI_GHES
int cxl_cper_register_work(struct work_struct *work);
int cxl_cper_unregister_work(struct work_struct *work);