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| author | Mario Limonciello <mario.limonciello@amd.com> | 2022-07-05 13:29:15 -0500 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2022-07-05 20:36:11 +0200 |
| commit | 8b356e536e69f3a4d6778ae9f0858a1beadabb1f (patch) | |
| tree | d94dad9bd21c339a808f95f19da24175ea79049b /include/acpi/processor.h | |
| parent | 7feec7430edddb87c24b0a86b08a03d0b496a755 (diff) | |
| download | lwn-8b356e536e69f3a4d6778ae9f0858a1beadabb1f.tar.gz lwn-8b356e536e69f3a4d6778ae9f0858a1beadabb1f.zip | |
ACPI: CPPC: Don't require _OSC if X86_FEATURE_CPPC is supported
commit 72f2ecb7ece7 ("ACPI: bus: Set CPPC _OSC bits for all and
when CPPC_LIB is supported") added support for claiming to
support CPPC in _OSC on non-Intel platforms.
This unfortunately caused a regression on a vartiety of AMD
platforms in the field because a number of AMD platforms don't set
the `_OSC` bit 5 or 6 to indicate CPPC or CPPC v2 support.
As these AMD platforms already claim CPPC support via a dedicated
MSR from `X86_FEATURE_CPPC`, use this enable this feature rather
than requiring the `_OSC` on platforms with a dedicated MSR.
If there is additional breakage on the shared memory designs also
missing this _OSC, additional follow up changes may be needed.
Fixes: 72f2ecb7ece7 ("Set CPPC _OSC bits for all and when CPPC_LIB is supported")
Reported-by: Perry Yuan <perry.yuan@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'include/acpi/processor.h')
0 files changed, 0 insertions, 0 deletions