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authorGil Fine <gil.fine@linux.intel.com>2023-01-25 11:48:14 +0200
committerMika Westerberg <mika.westerberg@linux.intel.com>2023-06-16 09:53:28 +0300
commit0209c808a56e6469f0ed50dd2e70c3aec074bf90 (patch)
tree364a4a9c83cc6135dd7697efeac02345e42bfe09 /drivers/thunderbolt
parent75abb4f5fff2314eef15887663a8dcfa062b4f67 (diff)
downloadlwn-0209c808a56e6469f0ed50dd2e70c3aec074bf90.tar.gz
lwn-0209c808a56e6469f0ed50dd2e70c3aec074bf90.zip
thunderbolt: Fix PCIe adapter capability length for USB4 v2 routers
For USB4 v2 routers, the PCIe adapter capability length is longer. Display the correct capability length in the debugfs register dump. Signed-off-by: Gil Fine <gil.fine@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/thunderbolt')
-rw-r--r--drivers/thunderbolt/debugfs.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/thunderbolt/debugfs.c b/drivers/thunderbolt/debugfs.c
index 78bcf77831fe..c9ddd49138d8 100644
--- a/drivers/thunderbolt/debugfs.c
+++ b/drivers/thunderbolt/debugfs.c
@@ -14,7 +14,8 @@
#include "tb.h"
#include "sb_regs.h"
-#define PORT_CAP_PCIE_LEN 1
+#define PORT_CAP_V1_PCIE_LEN 1
+#define PORT_CAP_V2_PCIE_LEN 2
#define PORT_CAP_POWER_LEN 2
#define PORT_CAP_LANE_LEN 3
#define PORT_CAP_USB3_LEN 5
@@ -1175,7 +1176,10 @@ static void port_cap_show(struct tb_port *port, struct seq_file *s,
case TB_PORT_CAP_ADAP:
if (tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) {
- length = PORT_CAP_PCIE_LEN;
+ if (usb4_switch_version(port->sw) < 2)
+ length = PORT_CAP_V1_PCIE_LEN;
+ else
+ length = PORT_CAP_V2_PCIE_LEN;
} else if (tb_port_is_dpin(port)) {
if (usb4_switch_version(port->sw) < 2)
length = PORT_CAP_DP_V1_LEN;