PCI: designware: Simplify dw_pcie_cfg_read/write() interfaces

Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to
split the address into "addr" and "where".  The callees assumed "addr" was
32-bit aligned (with zeros in the low two bits) and they used only the low
two bits of "where".

Accept the entire address in "addr" and drop the now-redundant "where"
argument.  As an example, this replaces this:

  int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
    *val = readb(addr + (where & 1));

with this:

  int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
    *val = readb(addr):

[bhelgaas: changelog, split access size change to separate patch]
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 35123d9362c5..e7b3279c3ff0 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -76,8 +76,8 @@ struct pcie_host_ops {
 	int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
 };
 
-int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
-int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
+int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);
+int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);