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author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-07-11 15:34:05 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-07-11 15:34:05 -0700 |
commit | 97ff4ca46d3279134cec49752de8c5a62dc68460 (patch) | |
tree | 3b562d5890b2fc358ca55a935395cc7938155406 /drivers/memory | |
parent | 4832a4dada1a2baefac76b70e4f3a78e71a7c35c (diff) | |
parent | 2f4281f4dce12440727ab770683cfb83eab62a26 (diff) | |
download | lwn-97ff4ca46d3279134cec49752de8c5a62dc68460.tar.gz lwn-97ff4ca46d3279134cec49752de8c5a62dc68460.zip |
Merge tag 'char-misc-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char / misc driver updates from Greg KH:
"Here is the "large" pull request for char and misc and other assorted
smaller driver subsystems for 5.3-rc1.
It seems that this tree is becoming the funnel point of lots of
smaller driver subsystems, which is fine for me, but that's why it is
getting larger over time and does not just contain stuff under
drivers/char/ and drivers/misc.
Lots of small updates all over the place here from different driver
subsystems:
- habana driver updates
- coresight driver updates
- documentation file movements and updates
- Android binder fixes and updates
- extcon driver updates
- google firmware driver updates
- fsi driver updates
- smaller misc and char driver updates
- soundwire driver updates
- nvmem driver updates
- w1 driver fixes
All of these have been in linux-next for a while with no reported
issues"
* tag 'char-misc-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (188 commits)
coresight: Do not default to CPU0 for missing CPU phandle
dt-bindings: coresight: Change CPU phandle to required property
ocxl: Allow contexts to be attached with a NULL mm
fsi: sbefifo: Don't fail operations when in SBE IPL state
coresight: tmc: Smatch: Fix potential NULL pointer dereference
coresight: etm3x: Smatch: Fix potential NULL pointer dereference
coresight: Potential uninitialized variable in probe()
coresight: etb10: Do not call smp_processor_id from preemptible
coresight: tmc-etf: Do not call smp_processor_id from preemptible
coresight: tmc-etr: alloc_perf_buf: Do not call smp_processor_id from preemptible
coresight: tmc-etr: Do not call smp_processor_id() from preemptible
docs: misc-devices: convert files without extension to ReST
fpga: dfl: fme: align PR buffer size per PR datawidth
fpga: dfl: fme: remove copy_to_user() in ioctl for PR
fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address.
intel_th: msu: Start read iterator from a non-empty window
intel_th: msu: Split sgt array and pointer in multiwindow mode
intel_th: msu: Support multipage blocks
intel_th: pci: Add Ice Lake NNPI support
intel_th: msu: Fix single mode with disabled IOMMU
...
Diffstat (limited to 'drivers/memory')
-rw-r--r-- | drivers/memory/Kconfig | 2 | ||||
-rw-r--r-- | drivers/memory/jz4780-nemc.c | 26 |
2 files changed, 23 insertions, 5 deletions
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 392ad4f5c570..dbdee02bb592 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -123,7 +123,7 @@ config FSL_IFC config JZ4780_NEMC bool "Ingenic JZ4780 SoC NEMC driver" default y - depends on MACH_JZ4780 || COMPILE_TEST + depends on MIPS || COMPILE_TEST depends on HAS_IOMEM && OF help This driver is for the NAND/External Memory Controller (NEMC) in diff --git a/drivers/memory/jz4780-nemc.c b/drivers/memory/jz4780-nemc.c index 698da973de35..2a3f7ef1c8c4 100644 --- a/drivers/memory/jz4780-nemc.c +++ b/drivers/memory/jz4780-nemc.c @@ -41,9 +41,14 @@ #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1) #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1) +struct jz_soc_info { + u8 tas_tah_cycles_max; +}; + struct jz4780_nemc { spinlock_t lock; struct device *dev; + const struct jz_soc_info *soc_info; void __iomem *base; struct clk *clk; uint32_t clk_period; @@ -158,7 +163,7 @@ static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc, * Conversion of tBP and tAW cycle counts to values supported by the * hardware (round up to the next supported value). */ - static const uint32_t convert_tBP_tAW[] = { + static const u8 convert_tBP_tAW[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, /* 11 - 12 -> 12 cycles */ @@ -199,7 +204,7 @@ static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc, if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) { smcr &= ~NEMC_SMCR_TAS_MASK; cycles = jz4780_nemc_ns_to_cycles(nemc, val); - if (cycles > 15) { + if (cycles > nemc->soc_info->tas_tah_cycles_max) { dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n", val, cycles); return false; @@ -211,7 +216,7 @@ static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc, if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) { smcr &= ~NEMC_SMCR_TAH_MASK; cycles = jz4780_nemc_ns_to_cycles(nemc, val); - if (cycles > 15) { + if (cycles > nemc->soc_info->tas_tah_cycles_max) { dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n", val, cycles); return false; @@ -275,6 +280,10 @@ static int jz4780_nemc_probe(struct platform_device *pdev) if (!nemc) return -ENOMEM; + nemc->soc_info = device_get_match_data(dev); + if (!nemc->soc_info) + return -EINVAL; + spin_lock_init(&nemc->lock); nemc->dev = dev; @@ -367,8 +376,17 @@ static int jz4780_nemc_remove(struct platform_device *pdev) return 0; } +static const struct jz_soc_info jz4740_soc_info = { + .tas_tah_cycles_max = 7, +}; + +static const struct jz_soc_info jz4780_soc_info = { + .tas_tah_cycles_max = 15, +}; + static const struct of_device_id jz4780_nemc_dt_match[] = { - { .compatible = "ingenic,jz4780-nemc" }, + { .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, }, + { .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, }, {}, }; |