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authorTom Saeger <tom.saeger@oracle.com>2021-03-12 19:31:10 -0700
committerJassi Brar <jaswinder.singh@linaro.org>2021-04-13 20:07:35 -0500
commit9d2e8b93236a45f20ae0b71cc507301111cc2f58 (patch)
tree6e24bf016583bd52b0d50f23a317b04a996712b6 /drivers/mailbox/bcm-flexrm-mailbox.c
parent3cfc7489667bcd2ab4eb1638ec7bc8b67c6324d0 (diff)
downloadlwn-9d2e8b93236a45f20ae0b71cc507301111cc2f58.tar.gz
lwn-9d2e8b93236a45f20ae0b71cc507301111cc2f58.zip
mailbox: fix various typos in comments
Fix trivial typos in mailbox driver comments. s/Intergrated/Integrated/ s/extenstion/extension/ s/atleast/at least/ s/commnunication/communication/ s/assgined/assigned/ s/commnunication/communication/ s/recevied/received/ s/succeded/succeeded/ s/implmentation/implementation/ s/definiation/definition/ s/traget/target/ s/wont/won't/ Cc: trivial@kernel.org Signed-off-by: Tom Saeger <tom.saeger@oracle.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Diffstat (limited to 'drivers/mailbox/bcm-flexrm-mailbox.c')
-rw-r--r--drivers/mailbox/bcm-flexrm-mailbox.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mailbox/bcm-flexrm-mailbox.c b/drivers/mailbox/bcm-flexrm-mailbox.c
index bee33abb5308..b4f33dc399a0 100644
--- a/drivers/mailbox/bcm-flexrm-mailbox.c
+++ b/drivers/mailbox/bcm-flexrm-mailbox.c
@@ -423,7 +423,7 @@ static void flexrm_enqueue_desc(u32 nhpos, u32 nhcnt, u32 reqid,
*
* In general use, number of non-HEADER descriptors can easily go
* beyond 31. To tackle this situation, we have packet (or request)
- * extenstion bits (STARTPKT and ENDPKT) in the HEADER descriptor.
+ * extension bits (STARTPKT and ENDPKT) in the HEADER descriptor.
*
* To use packet extension, the first HEADER descriptor of request
* (or packet) will have STARTPKT=1 and ENDPKT=0. The intermediate
@@ -1095,7 +1095,7 @@ static int flexrm_process_completions(struct flexrm_ring *ring)
/*
* Get current completion read and write offset
*
- * Note: We should read completion write pointer atleast once
+ * Note: We should read completion write pointer at least once
* after we get a MSI interrupt because HW maintains internal
* MSI status which will allow next MSI interrupt only after
* completion write pointer is read.