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authorMatt Roper <matthew.d.roper@intel.com>2023-07-28 10:56:02 -0700
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-21 11:39:16 -0500
commitfe58a2432b0d07cf56704ecf1ca5e52e6c1e8fff (patch)
treeda590440b48ccf6805baf44ad5203d328b057007 /drivers/gpu/drm/xe/xe_wa.c
parentd87c424afaf62f11ded6e66b4bdfbd5f5da8b330 (diff)
downloadlwn-fe58a2432b0d07cf56704ecf1ca5e52e6c1e8fff.tar.gz
lwn-fe58a2432b0d07cf56704ecf1ca5e52e6c1e8fff.zip
drm/xe/mtl: Reduce Wa_14018575942 scope to the CCS engine
The MTL version of Wa_14018575942 has been updated to suggest only applying the register change on the CCS engine. Note that DG2 and PVC have a functionally equivalent workaround with Wa_18018781329; for now that one is still applying to all engines, although we'll keep an eye on it in case it changes to be CCS-specific too. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/20230728175601.2343755-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_wa.c')
-rw-r--r--drivers/gpu/drm/xe/xe_wa.c10
1 files changed, 1 insertions, 9 deletions
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 21087f7a4609..36c80e9fb758 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -238,21 +238,13 @@ static const struct xe_rtp_entry_sr gt_was[] = {
},
{ XE_RTP_NAME("14018575942"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
- XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
- SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
+ XE_RTP_ACTIONS(SET(COMP_MOD_CTRL, FORCE_MISS_FTLB))
},
{ XE_RTP_NAME("22016670082"),
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271)),
XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
},
- /* Xe_LPM+ */
- { XE_RTP_NAME("14018575942"),
- XE_RTP_RULES(MEDIA_VERSION(1300)),
- XE_RTP_ACTIONS(SET(XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
- SET(XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
- },
-
{}
};