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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-03-06 13:24:50 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-19 18:29:44 -0500 |
| commit | cedbc0b75790a1ee4f0bad0124c84b6813c2ef8c (patch) | |
| tree | 9b2205b911bed83fdbf8b472d066386ff9ca8212 /drivers/gpu/drm/xe/xe_wa.c | |
| parent | 63239946bc0101c2b10c119c77cd4b132d2c6484 (diff) | |
| download | lwn-cedbc0b75790a1ee4f0bad0124c84b6813c2ef8c.tar.gz lwn-cedbc0b75790a1ee4f0bad0124c84b6813c2ef8c.zip | |
drm/xe: Fix duplicated setting for register 0x6604
The following warning shows up for TGL:
[drm:xe_reg_sr_add [xe]] *ERROR* Discarding save-restore reg 6604 (clear: 00ff0000, set: 00040000, masked: no): ret=-22
[drm:xe_reg_sr_add [xe]] *ERROR* Discarding save-restore reg 6604 (clear: 00ff0000, set: 00040000, masked: no): ret=-22
That is because the same register is being set both by the WAs and the
tunings. Like was done in i915, prefer the tuning over the workaround
since that is applicable for more platforms. Also fix the tuning: it
was incorrectly using the MCR version of the register, but that only
became true in XEHP.
References: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/233
Reported-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/20230306212450.803557-1-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_wa.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_wa.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index df72b15dfeb0..71e9e1a111f8 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -265,13 +265,9 @@ static const struct xe_rtp_entry lrc_was[] = { GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL, XE_RTP_ACTION_FLAG(MASKED_REG))) }, - { XE_RTP_NAME("16011163337"), - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)), - /* read verification is ignored due to 1608008084. */ - XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(GEN12_FF_MODE2, - FF_MODE2_GS_TIMER_MASK, - FF_MODE2_GS_TIMER_224)) - }, + + /* DG1 */ + { XE_RTP_NAME("1409044764"), XE_RTP_RULES(PLATFORM(DG1)), XE_RTP_ACTIONS(CLR(GEN11_COMMON_SLICE_CHICKEN3, |