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authorHimal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>2024-04-01 22:08:06 +0530
committerMatt Roper <matthew.d.roper@intel.com>2024-04-02 12:11:41 -0700
commit9f18b55b6d3f77b9e778257efdec385d2d5dfa8e (patch)
tree0111fdaaa59c1bd9f443c69b658f11cc80fa1b0a /drivers/gpu/drm/xe/xe_wa.c
parent62742d12663145160d3b6f0c4209709c1fd343fe (diff)
downloadlwn-9f18b55b6d3f77b9e778257efdec385d2d5dfa8e.tar.gz
lwn-9f18b55b6d3f77b9e778257efdec385d2d5dfa8e.zip
drm/xe/xe2: Add workaround 18033852989
This workaround applies to RCS engine's context, hence added as LRC workaround. v2 - Fix commit description as lrc workaround instead of engine.(Lucas) v3 - COMMON_SLICE_CHICKEN1 is a masked register, add XE_REG_OPTION_MASKED flag. (Matt) BSPEC: 55899 Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240401163806.3821128-1-himal.prasad.ghimiray@intel.com
Diffstat (limited to 'drivers/gpu/drm/xe/xe_wa.c')
-rw-r--r--drivers/gpu/drm/xe/xe_wa.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 74b33a3845f2..c904e55ced9c 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -579,6 +579,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
ENGINE_CLASS(RENDER)),
XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT))
},
+ { XE_RTP_NAME("18033852989"),
+ XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
+ XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1, DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
+ },
{}
};