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| author | Tejas Upadhyay <tejas.upadhyay@intel.com> | 2023-12-05 10:51:59 +0530 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:45:24 -0500 |
| commit | 6a1fd6787d59a1852e89a9e8863673ae4dc9a2ca (patch) | |
| tree | 76a356d6edfe9cd251452a80c42f7e49e9868279 /drivers/gpu/drm/xe/xe_wa.c | |
| parent | d8b1571312b7f77aeae2b2a7a138bb8edaa4f725 (diff) | |
| download | lwn-6a1fd6787d59a1852e89a9e8863673ae4dc9a2ca.tar.gz lwn-6a1fd6787d59a1852e89a9e8863673ae4dc9a2ca.zip | |
drm/xe/xe2: Add workaround 14019988906
This workaround applies to Graphics 20.04 as engine
workaround
V2(MattR):
- Reorder bit define
- Apply WA for RCS only
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_wa.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_wa.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index 63bd4bb1af03..ce897f2d49be 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -719,6 +719,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = { ENGINE_CLASS(RENDER)), XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) }, + { XE_RTP_NAME("14019988906"), + XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)), + XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) + }, {} }; |