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| author | Haridhar Kalvala <haridhar.kalvala@intel.com> | 2023-11-08 13:03:51 +0530 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:43:38 -0500 |
| commit | 047d1f6a2f171fc9ea4c286edd6ee0dfef41a298 (patch) | |
| tree | e824c12997677406fdc7b18aa07a8a843201a27d /drivers/gpu/drm/xe/xe_wa.c | |
| parent | d7925d04c062b8adcbbff9604422f979e9dbedb7 (diff) | |
| download | lwn-047d1f6a2f171fc9ea4c286edd6ee0dfef41a298.tar.gz lwn-047d1f6a2f171fc9ea4c286edd6ee0dfef41a298.zip | |
drm/xe: Add Wa_14019877138
Enable Force Dispatch Ends Collection for DG2.
BSpec: 46001
Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231108073351.3998413-1-haridhar.kalvala@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_wa.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_wa.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index 614e114a5342..d03e6674519f 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -677,6 +677,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = { XE_RTP_RULES(PLATFORM(DG2)), XE_RTP_ACTIONS(SET(CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE)) }, + { XE_RTP_NAME("14019877138"), + XE_RTP_RULES(PLATFORM(DG2)), + XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) + }, /* PVC */ |