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authorMatt Roper <matthew.d.roper@intel.com>2024-08-29 15:06:21 -0700
committerMatt Roper <matthew.d.roper@intel.com>2024-08-30 08:56:20 -0700
commit3034cc8107b8d0c7d1b56584394e215dab57f8a3 (patch)
tree894bb987beec8c164b14cdf4daed92067c47f334 /drivers/gpu/drm/xe/xe_tile.c
parentcad08fa7760ace5e01b24c6f9e1f918fe72324bf (diff)
downloadlwn-3034cc8107b8d0c7d1b56584394e215dab57f8a3.tar.gz
lwn-3034cc8107b8d0c7d1b56584394e215dab57f8a3.zip
drm/xe/pcode: Treat pcode as per-tile rather than per-GT
There's only one instance of the pcode per tile, and for GT-related accesses both the primary and media GT share the same register interface. Since Xe was using per-GT locking, the pcode mutex wasn't actually protecting everything that it should since concurrent accesses related to a tile's primary GT and media GT were possible. Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs") Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240829220619.789159-5-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/xe/xe_tile.c')
-rw-r--r--drivers/gpu/drm/xe/xe_tile.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
index 15ea0a942f67..dda5268507d8 100644
--- a/drivers/gpu/drm/xe/xe_tile.c
+++ b/drivers/gpu/drm/xe/xe_tile.c
@@ -9,6 +9,7 @@
#include "xe_ggtt.h"
#include "xe_gt.h"
#include "xe_migrate.h"
+#include "xe_pcode.h"
#include "xe_sa.h"
#include "xe_tile.h"
#include "xe_tile_sysfs.h"
@@ -124,6 +125,8 @@ int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id)
if (IS_ERR(tile->primary_gt))
return PTR_ERR(tile->primary_gt);
+ xe_pcode_init(tile);
+
return 0;
}