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authorNiranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>2024-05-07 15:42:51 -0700
committerMatt Roper <matthew.d.roper@intel.com>2024-05-08 14:48:30 -0700
commitd6219e1cd5e321351954e317b362db2c1d34402a (patch)
treeb8420d3d34ab4ffda3cb87698e08f3ebc34e4512 /drivers/gpu/drm/xe/xe_guc_submit.c
parent85cfc412579c041f1aaebba71427acec75ceca39 (diff)
downloadlwn-d6219e1cd5e321351954e317b362db2c1d34402a.tar.gz
lwn-d6219e1cd5e321351954e317b362db2c1d34402a.zip
drm/xe: Add Indirect Ring State support
When Indirect Ring State is enabled, the Ring Buffer state and Batch Buffer state are context save/restored to/from Indirect Ring State instead of the LRC. The Indirect Ring State is a 4K page mapped in global GTT at a 4K aligned address. This address is programmed in the INDIRECT_RING_STATE register of the corresponding context's LRC. v2: Fix kernel-doc, add bspec reference v3: Fix typo in commit text Bspec: 67296, 67139 Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240507224255.5059-3-niranjana.vishwanathapura@intel.com
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc_submit.c')
-rw-r--r--drivers/gpu/drm/xe/xe_guc_submit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 2c0aa3443cd9..fde527d34f58 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -677,7 +677,7 @@ static void submit_exec_queue(struct xe_exec_queue *q)
if (xe_exec_queue_is_parallel(q))
wq_item_append(q);
else
- xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
+ xe_lrc_set_ring_tail(lrc, lrc->ring.tail);
if (exec_queue_suspended(q) && !xe_exec_queue_is_parallel(q))
return;