diff options
| author | Badal Nilawar <badal.nilawar@intel.com> | 2023-11-01 22:02:12 +0530 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:43:33 -0500 |
| commit | effc560d7a36b8c59219dd5374d9725a9edd85c4 (patch) | |
| tree | 759675c63a9bd953a66df3a44f8c95d4046c0db6 /drivers/gpu/drm/xe/xe_guc_pc.c | |
| parent | 4d5252b4ca1dc973b8b368c88f9d1e348f9c1906 (diff) | |
| download | lwn-effc560d7a36b8c59219dd5374d9725a9edd85c4.tar.gz lwn-effc560d7a36b8c59219dd5374d9725a9edd85c4.zip | |
drm/xe/mtl: Use 16.67 Mhz freq scale factor to get rpX
For mtl and above 16.67 Mhz is the scale factor to calculate
rpX frequencies.
v2: Fix review comment (Ashutosh)
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231101163212.1629685-1-badal.nilawar@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_guc_pc.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_guc_pc.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c index 74247e0d3674..020c6597cd78 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.c +++ b/drivers/gpu/drm/xe/xe_guc_pc.c @@ -313,7 +313,7 @@ static void mtl_update_rpe_value(struct xe_guc_pc *pc) else reg = xe_mmio_read32(gt, MTL_GT_RPE_FREQUENCY); - pc->rpe_freq = REG_FIELD_GET(MTL_RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER; + pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg)); } static void tgl_update_rpe_value(struct xe_guc_pc *pc) @@ -653,10 +653,10 @@ static void mtl_init_fused_rp_values(struct xe_guc_pc *pc) reg = xe_mmio_read32(gt, MTL_MEDIAP_STATE_CAP); else reg = xe_mmio_read32(gt, MTL_RP_STATE_CAP); - pc->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, reg) * - GT_FREQUENCY_MULTIPLIER; - pc->rpn_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, reg) * - GT_FREQUENCY_MULTIPLIER; + + pc->rp0_freq = decode_freq(REG_FIELD_GET(MTL_RP0_CAP_MASK, reg)); + + pc->rpn_freq = decode_freq(REG_FIELD_GET(MTL_RPN_CAP_MASK, reg)); } static void tgl_init_fused_rp_values(struct xe_guc_pc *pc) |