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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-04-27 15:32:48 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-19 18:32:15 -0500 |
| commit | d9b79ad275e7a98c566b3ac4b32950142d6bf9ad (patch) | |
| tree | 787a2885b7b78c60c71bb33345d61f09a7c3926b /drivers/gpu/drm/xe/xe_ggtt.c | |
| parent | 7b829f6dd638c2cb45c7710bc7cd1d0395ea9bc1 (diff) | |
| download | lwn-d9b79ad275e7a98c566b3ac4b32950142d6bf9ad.tar.gz lwn-d9b79ad275e7a98c566b3ac4b32950142d6bf9ad.zip | |
drm/xe: Drop gen afixes from registers
The defines for the registers were brought over from i915 while
bootstrapping the driver. As xe supports TGL and later only, it doesn't
make sense to keep the GEN* prefixes and suffixes in the registers: TGL
is graphics version 12, previously called "GEN12". So drop the prefix
everywhere.
v2:
- Also drop _TGL suffix and reword commit message as suggested
by Matt Roper. While at it, rename VSUNIT_CLKGATE_DIS_TGL to
VSUNIT_CLKGATE2_DIS with the additional "2", so it doesn't clash
with the define for the other register
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230427223256.1432787-3-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_ggtt.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_ggtt.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c index 10a262a0c4cd..fc580d961dbb 100644 --- a/drivers/gpu/drm/xe/xe_ggtt.c +++ b/drivers/gpu/drm/xe/xe_ggtt.c @@ -185,12 +185,12 @@ err: return err; } -#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8) -#define GEN12_GUC_TLB_INV_CR_INVALIDATE REG_BIT(0) +#define GUC_TLB_INV_CR _MMIO(0xcee8) +#define GUC_TLB_INV_CR_INVALIDATE REG_BIT(0) #define PVC_GUC_TLB_INV_DESC0 _MMIO(0xcf7c) -#define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0) +#define PVC_GUC_TLB_INV_DESC0_VALID REG_BIT(0) #define PVC_GUC_TLB_INV_DESC1 _MMIO(0xcf80) -#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6) +#define PVC_GUC_TLB_INV_DESC1_INVALIDATE REG_BIT(6) void xe_ggtt_invalidate(struct xe_gt *gt) { @@ -212,8 +212,8 @@ void xe_ggtt_invalidate(struct xe_gt *gt) xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0.reg, PVC_GUC_TLB_INV_DESC0_VALID); } else - xe_mmio_write32(gt, GEN12_GUC_TLB_INV_CR.reg, - GEN12_GUC_TLB_INV_CR_INVALIDATE); + xe_mmio_write32(gt, GUC_TLB_INV_CR.reg, + GUC_TLB_INV_CR_INVALIDATE); } } |