diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2023-03-31 17:21:00 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-19 18:31:30 -0500 |
| commit | 9293b67de6602bcf0415da0f3ae3dbf98396183c (patch) | |
| tree | 51ccfeebbcaf98cd01ce8c4d112a77fe32952b58 /drivers/gpu/drm/xe/regs/xe_regs.h | |
| parent | 06d06064f725c207a4d14b7410f5498d68c1fb86 (diff) | |
| download | lwn-9293b67de6602bcf0415da0f3ae3dbf98396183c.tar.gz lwn-9293b67de6602bcf0415da0f3ae3dbf98396183c.zip | |
drm/xe/irq: Add helpers to find ISR/IIR/IMR/IER registers
For cases where IRQ_INIT and IRQ_RESET are used, the relevant interrupt
registers are always consecutive and ordered ISR, IMR, IIR, IER. Adding
helpers to look these up from a base offset will let us eliminate some
of the CPP pasting and simplify other upcoming patches.
v2:
- s/_REGS/_OFFSET/ for consistency. (Lucas)
- Move IMR/IIR/IER helpers into xe_irq.c; they aren't needed anywhere
else. (Lucas)
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230401002106.588656-3-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs/xe_regs.h')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_regs.h | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index 2e7fbdedb5eb..61b6b356c90e 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -72,15 +72,8 @@ #define SOFTWARE_FLAGS_SPR33 _MMIO(0x4f084) -#define GEN8_PCU_ISR _MMIO(0x444e0) -#define GEN8_PCU_IMR _MMIO(0x444e4) -#define GEN8_PCU_IIR _MMIO(0x444e8) -#define GEN8_PCU_IER _MMIO(0x444ec) - -#define GEN11_GU_MISC_ISR _MMIO(0x444f0) -#define GEN11_GU_MISC_IMR _MMIO(0x444f4) -#define GEN11_GU_MISC_IIR _MMIO(0x444f8) -#define GEN11_GU_MISC_IER _MMIO(0x444fc) +#define PCU_IRQ_OFFSET 0x444e0 +#define GU_MISC_IRQ_OFFSET 0x444f0 #define GEN11_GU_MISC_GSE (1 << 27) #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) |