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| author | Tejas Upadhyay <tejas.upadhyay@intel.com> | 2024-08-14 15:26:14 +0530 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2024-08-14 12:29:09 -0700 |
| commit | 4551d60299b5ddc2655b6b365a4b92634e14e04f (patch) | |
| tree | 6a8853d3ff225c5bb8748de7cf35af63cc5c3522 /drivers/gpu/drm/xe/regs/xe_gt_regs.h | |
| parent | f0ffa657e9f3913c7921cbd4d876343401f15f52 (diff) | |
| download | lwn-4551d60299b5ddc2655b6b365a4b92634e14e04f.tar.gz lwn-4551d60299b5ddc2655b6b365a4b92634e14e04f.zip | |
drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register
Register STATELESS_COMPRESSION_CTRL should be considered
mcr register which should write to all slices as per
documentation.
Bspec: 71185
Fixes: ecabb5e6ce54 ("drm/xe/xe2: Add performance turning changes")
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240814095614.909774-4-tejas.upadhyay@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs/xe_gt_regs.h')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index aeb17fcb27ac..0d1a4a9f4e11 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -80,7 +80,7 @@ #define LE_CACHEABILITY_MASK REG_GENMASK(1, 0) #define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value) -#define STATELESS_COMPRESSION_CTRL XE_REG(0x4148) +#define STATELESS_COMPRESSION_CTRL XE_REG_MCR(0x4148) #define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0) #define XE2_GAMREQSTRM_CTRL XE_REG_MCR(0x4194) |