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authorDave Airlie <airlied@redhat.com>2010-02-15 15:54:45 +1000
committerDave Airlie <airlied@redhat.com>2010-02-15 15:54:45 +1000
commit2e98f10a7a87ebae4dcc3949028a32008b46ceef (patch)
treecf2b173d7f04592f3c8d70d3457436a289c45e57 /drivers/gpu/drm/radeon/r600.c
parent7cb72ef4d39978e6e07415a2d552b06d567c3079 (diff)
downloadlwn-2e98f10a7a87ebae4dcc3949028a32008b46ceef.tar.gz
lwn-2e98f10a7a87ebae4dcc3949028a32008b46ceef.zip
drm/radeon/kms: flush HDP cache on GART table updates.
Suggested by Alex Deucher @ AMD Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 4facbab20456..6434d6af7d52 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -370,6 +370,9 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
unsigned i;
u32 tmp;
+ /* flush hdp cache so updates hit vram */
+ WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+
WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));