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| author | Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> | 2022-02-11 09:58:49 -0500 |
|---|---|---|
| committer | Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> | 2022-02-11 11:43:48 -0500 |
| commit | 2e87309e0660fed736ca5823b714c1d958941c4d (patch) | |
| tree | c792e455d2514ab7563114779c73db92d281946e /drivers/gpu/drm/panfrost/panfrost_features.h | |
| parent | 721255b52700b320c4ae2e23d57f7d9ad1db50b9 (diff) | |
| download | lwn-2e87309e0660fed736ca5823b714c1d958941c4d.tar.gz lwn-2e87309e0660fed736ca5823b714c1d958941c4d.zip | |
drm/panfrost: Handle IDVS_GROUP_SIZE feature
The IDVS group size feature was missing. It is used on some Bifrost and
Valhall GPUs, and is the last kernel-relevant Bifrost feature we're
missing.
This feature adds an extra IDVS group size field to the JM_CONFIG
register. In kbase, the value is configurable via the device tree; kbase
uses 0xF as a default if no value is specified. Until we find a device
demanding otherwise, let's always set the 0xF default on devices which
support this feature mimicking kbase's behaviour.
Tuning this register slightly improves performance of index-driven
vertex shading. On Mali-G52 (with Mesa), overall glmark2 score is
improved from 1026 to 1037. Geometry-heavy scenes like -bshading are
improved from 1068 to 1098.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220211145849.3148-1-alyssa.rosenzweig@collabora.com
Diffstat (limited to 'drivers/gpu/drm/panfrost/panfrost_features.h')
| -rw-r--r-- | drivers/gpu/drm/panfrost/panfrost_features.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/panfrost/panfrost_features.h b/drivers/gpu/drm/panfrost/panfrost_features.h index 34f2bae1ec8c..36fadcf9634e 100644 --- a/drivers/gpu/drm/panfrost/panfrost_features.h +++ b/drivers/gpu/drm/panfrost/panfrost_features.h @@ -20,6 +20,7 @@ enum panfrost_hw_feature { HW_FEATURE_AARCH64_MMU, HW_FEATURE_TLS_HASHING, HW_FEATURE_THREAD_GROUP_SPLIT, + HW_FEATURE_IDVS_GROUP_SIZE, HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG, }; @@ -74,6 +75,7 @@ enum panfrost_hw_feature { BIT_ULL(HW_FEATURE_FLUSH_REDUCTION) | \ BIT_ULL(HW_FEATURE_PROTECTED_MODE) | \ BIT_ULL(HW_FEATURE_PROTECTED_DEBUG_MODE) | \ + BIT_ULL(HW_FEATURE_IDVS_GROUP_SIZE) | \ BIT_ULL(HW_FEATURE_COHERENCY_REG)) #define hw_features_g76 (\ @@ -87,6 +89,7 @@ enum panfrost_hw_feature { BIT_ULL(HW_FEATURE_COHERENCY_REG) | \ BIT_ULL(HW_FEATURE_AARCH64_MMU) | \ BIT_ULL(HW_FEATURE_TLS_HASHING) | \ + BIT_ULL(HW_FEATURE_IDVS_GROUP_SIZE) | \ BIT_ULL(HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG)) #define hw_features_g31 (\ |