diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2020-03-06 10:08:10 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2020-03-06 10:08:10 +0800 |
| commit | a61ac1e75105a077ec1efd6923ae3c619f862304 (patch) | |
| tree | 31a24e8ae27e3d124e237802c403746dc5108ee2 /drivers/gpu/drm/i915/gvt/mmio.c | |
| parent | 8fde41076f6df53db84cb13051efed6482986ce3 (diff) | |
| download | lwn-a61ac1e75105a077ec1efd6923ae3c619f862304.tar.gz lwn-a61ac1e75105a077ec1efd6923ae3c619f862304.zip | |
drm/i915/gvt: Wean gvt off using dev_priv
Teach gvt to use intel_gt directly as it currently assumes direct HW
access.
[Zhenyu: rebase, fix compiling]
Cc: Ding Zhuocheng <zhuocheng.ding@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200304032307.2983-3-zhenyuw@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/mmio.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/mmio.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c index 1046a68da888..291993615af9 100644 --- a/drivers/gpu/drm/i915/gvt/mmio.c +++ b/drivers/gpu/drm/i915/gvt/mmio.c @@ -102,8 +102,8 @@ static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa, int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa, void *p_data, unsigned int bytes) { - struct drm_i915_private *i915 = vgpu->gvt->dev_priv; struct intel_gvt *gvt = vgpu->gvt; + struct drm_i915_private *i915 = gvt->gt->i915; unsigned int offset = 0; int ret = -EINVAL; @@ -177,8 +177,8 @@ out: int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa, void *p_data, unsigned int bytes) { - struct drm_i915_private *i915 = vgpu->gvt->dev_priv; struct intel_gvt *gvt = vgpu->gvt; + struct drm_i915_private *i915 = gvt->gt->i915; unsigned int offset = 0; int ret = -EINVAL; @@ -251,7 +251,7 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr) /* set the bit 0:2(Core C-State ) to C0 */ vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; - if (IS_BROXTON(vgpu->gvt->dev_priv)) { + if (IS_BROXTON(vgpu->gvt->gt->i915)) { vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1)); vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= |