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| author | Jani Nikula <jani.nikula@intel.com> | 2024-06-04 18:26:12 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2024-06-07 11:28:59 +0300 |
| commit | 3c461986e8ab2bc126a2bb7868b4f9f3b125e965 (patch) | |
| tree | d149b96effd12a2873bd89e0ab8bc2274a8957b7 /drivers/gpu/drm/i915/gvt/display.c | |
| parent | 9ffd21103d064c382110bd0c4bdec0c2a4db9960 (diff) | |
| download | lwn-3c461986e8ab2bc126a2bb7868b4f9f3b125e965.tar.gz lwn-3c461986e8ab2bc126a2bb7868b4f9f3b125e965.zip | |
drm/i915: pass dev_priv explicitly to PIPE_LINK_M1
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_LINK_M1 register macro.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/bf25d447d98009f56f2c5b2205719ab2d9a70c93.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/display.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 5f3ee57b5982..eea956603cc8 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -264,7 +264,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; - vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; + vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; /* Enable per-DDI/PORT vreg */ @@ -398,7 +398,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; - vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; + vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; } |