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authorJinZe.Xu <JinZe.Xu@amd.com>2023-04-10 23:23:37 +0800
committerAlex Deucher <alexander.deucher@amd.com>2023-04-24 18:36:45 -0400
commit8f3589bb6fcea397775398cba4fbcc46829a60ed (patch)
tree93010984864e0025518e17a704dd3198c0edcde5 /drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
parent278d3de6754e778cb676b7e1b10782eff1971010 (diff)
downloadlwn-8f3589bb6fcea397775398cba4fbcc46829a60ed.tar.gz
lwn-8f3589bb6fcea397775398cba4fbcc46829a60ed.zip
drm/amd/display: Restore rptr/wptr for DMCUB as workaround
[Why] States may be desync after resume. [How] Sync sw state with hw state. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: JinZe.Xu <JinZe.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c')
-rw-r--r--drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
index a7d5607459ed..21dd6cbdb106 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -266,6 +266,11 @@ void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,
REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
}
+uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub)
+{
+ return REG_READ(DMCUB_INBOX1_WPTR);
+}
+
uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub)
{
return REG_READ(DMCUB_INBOX1_RPTR);