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| author | Aakash Menon <aakash.r.menon@gmail.com> | 2024-09-16 22:18:29 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2024-09-22 19:53:19 +0100 |
| commit | 151ac45348afc5b56baa584c7cd4876addf461ff (patch) | |
| tree | 48f7bb9735790c65018430669773e9ce24ff7c37 /drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c | |
| parent | 9410645520e9b820069761f3450ef6661418e279 (diff) | |
| download | lwn-151ac45348afc5b56baa584c7cd4876addf461ff.tar.gz lwn-151ac45348afc5b56baa584c7cd4876addf461ff.zip | |
net: sparx5: Fix invalid timestamps
Bit 270-271 are occasionally unexpectedly set by the hardware. This issue
was observed with 10G SFPs causing huge time errors (> 30ms) in PTP. Only
30 bits are needed for the nanosecond part of the timestamp, clear 2 most
significant bits before extracting timestamp from the internal frame
header.
Fixes: 70dfe25cd866 ("net: sparx5: Update extraction/injection for timestamping")
Signed-off-by: Aakash Menon <aakash.menon@protempis.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c')
0 files changed, 0 insertions, 0 deletions