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| author | Piotr Redlewski <predlewski@gmail.com> | 2017-11-10 19:28:01 +0100 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-06 12:47:22 -0500 |
| commit | c1fe75c9e42c8c598a7fb810ecc4f7be258e700c (patch) | |
| tree | 3193f160fa5826c52f23f64181dfd00c5925c7ec /drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | |
| parent | fa2123dbccdc881fae02aaf8b05758db53d62955 (diff) | |
| download | lwn-c1fe75c9e42c8c598a7fb810ecc4f7be258e700c.tar.gz lwn-c1fe75c9e42c8c598a7fb810ecc4f7be258e700c.zip | |
drm/amd/amdgpu: fix UVD mc offsets
When UVD bo is created, its size is based on the information from firmware
header (ucode_size_bytes). The same value should be be used when programming
UVD mc controller offsets, otherwise it can happen that
(mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point
AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end.
Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register,
AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't,
(mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point
AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end.
v2: move firmware size calculation into macro definition
v3: align firmware size to the gpu page size
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Piotr Redlewski <predlewski@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 15771a53038e..b13ae34be1c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -563,7 +563,7 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) /* programm the VCPU memory controller bits 0-27 */ addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; - size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; + size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); WREG32(mmUVD_VCPU_CACHE_SIZE0, size); |