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| author | Likun Gao <Likun.Gao@amd.com> | 2020-04-17 17:33:35 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:13 -0400 |
| commit | f64668f9aab67136fa537a26d9ad51fdb2b33c3d (patch) | |
| tree | 6e3ea00b3d011b469451b60b23b14f15965358d7 /drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | |
| parent | 338d90b613ea3546faeb55a94850d997c9a61689 (diff) | |
| download | lwn-f64668f9aab67136fa537a26d9ad51fdb2b33c3d.tar.gz lwn-f64668f9aab67136fa537a26d9ad51fdb2b33c3d.zip | |
drm/amdgpu: only use one gfx pipe for Sienna_Cichlid
Only enable one gfx pipe for sienna_cichlid currently.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index f0955b325798..cc1835cd0c91 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -55,7 +55,7 @@ * 2. Async ring */ #define GFX10_NUM_GFX_RINGS_NV1X 1 -#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 +#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1 #define GFX10_MEC_HPD_SIZE 2048 #define F32_CE_PROGRAM_RAM_SIZE 65536 @@ -4232,7 +4232,7 @@ static int gfx_v10_0_sw_init(void *handle) break; case CHIP_SIENNA_CICHLID: adev->gfx.me.num_me = 1; - adev->gfx.me.num_pipe_per_me = 2; + adev->gfx.me.num_pipe_per_me = 1; adev->gfx.me.num_queue_per_pipe = 1; adev->gfx.mec.num_mec = 2; adev->gfx.mec.num_pipe_per_mec = 4; |