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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2023-05-26 10:58:22 +0100 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-05-30 11:20:35 -0700 |
| commit | 1ad3f701c3999904d0c6cdea299df16c6cd9878d (patch) | |
| tree | 7c33090738ab6fb1e3a6ad656585ba3089d5d128 /drivers/cxl/pmu.h | |
| parent | d717d7f3df18494baafd9595fb4bcb9c380d7389 (diff) | |
| download | lwn-1ad3f701c3999904d0c6cdea299df16c6cd9878d.tar.gz lwn-1ad3f701c3999904d0c6cdea299df16c6cd9878d.zip | |
cxl/pci: Find and register CXL PMU devices
CXL PMU devices can be found from entries in the Register
Locator DVSEC.
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230526095824.16336-4-Jonathan.Cameron@huawei.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/pmu.h')
| -rw-r--r-- | drivers/cxl/pmu.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/cxl/pmu.h b/drivers/cxl/pmu.h new file mode 100644 index 000000000000..b1e9bcd9f28c --- /dev/null +++ b/drivers/cxl/pmu.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright(c) 2023 Huawei + * CXL Specification rev 3.0 Setion 8.2.7 (CPMU Register Interface) + */ +#ifndef CXL_PMU_H +#define CXL_PMU_H +#include <linux/device.h> + +enum cxl_pmu_type { + CXL_PMU_MEMDEV, +}; + +#define CXL_PMU_REGMAP_SIZE 0xe00 /* Table 8-32 CXL 3.0 specification */ +struct cxl_pmu { + struct device dev; + void __iomem *base; + int assoc_id; + int index; + enum cxl_pmu_type type; +}; + +#define to_cxl_pmu(dev) container_of(dev, struct cxl_pmu, dev) +struct cxl_pmu_regs; +int devm_cxl_pmu_add(struct device *parent, struct cxl_pmu_regs *regs, + int assoc_id, int idx, enum cxl_pmu_type type); + +#endif |