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| author | Robert Richter <rrichter@amd.com> | 2023-10-18 19:17:00 +0200 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-10-27 20:13:37 -0700 |
| commit | 8ce520fdea245c9e17ebc0659973984362bc1fde (patch) | |
| tree | bb37fdc716e7beadf0177d6c6804ffa2effa7b19 /drivers/cxl/mem.c | |
| parent | 2dd18279202f6247904e6e23738c1ec6a86b24b1 (diff) | |
| download | lwn-8ce520fdea245c9e17ebc0659973984362bc1fde.tar.gz lwn-8ce520fdea245c9e17ebc0659973984362bc1fde.zip | |
cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
Now, that the Component Register mappings are stored, use them to
enable and map the HDM decoder capabilities. The Component Registers
do not need to be probed again for this, remove probing code.
The HDM capability applies to Endpoints, USPs and VH Host Bridges. The
Endpoint's component register mappings are located in the cxlds and
else in the port's structure. Duplicate the cxlds->reg_map in
port->reg_map for endpoint ports.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
[rework to drop cxl_port_get_comp_map()]
Link: https://lore.kernel.org/r/20231018171713.1883517-8-rrichter@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/mem.c')
| -rw-r--r-- | drivers/cxl/mem.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 317c7548e4e9..04107058739b 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -49,7 +49,6 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, struct cxl_dport *parent_dport) { struct cxl_port *parent_port = parent_dport->port; - struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_port *endpoint, *iter, *down; int rc; @@ -65,8 +64,8 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, ep->next = down; } - endpoint = devm_cxl_add_port(host, &cxlmd->dev, - cxlds->component_reg_phys, + /* Note: endpoint port component registers are derived from @cxlds */ + endpoint = devm_cxl_add_port(host, &cxlmd->dev, CXL_RESOURCE_NONE, parent_dport); if (IS_ERR(endpoint)) return PTR_ERR(endpoint); |