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| author | Jagadeesh Kona <quic_jkona@quicinc.com> | 2024-06-02 17:14:34 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-06-25 18:06:25 -0500 |
| commit | 6e18795a6acfd04cec3af23680e9051237d4fa94 (patch) | |
| tree | 65b3c3df68fba392bbde5766847ad71832dc9911 /drivers/clk | |
| parent | a6a61b9701d1add3bb6d86d8e259d833ea91a1a6 (diff) | |
| download | lwn-6e18795a6acfd04cec3af23680e9051237d4fa94.tar.gz lwn-6e18795a6acfd04cec3af23680e9051237d4fa94.zip | |
clk: qcom: videocc-sm8550: Add support for videocc XO clk ares
Add support for videocc XO clk ares for consumer drivers to be
able to request this reset.
Fixes: f53153a37969 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550")
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240602114439.1611-4-quic_jkona@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/videocc-sm8550.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index d73f747d2474..25133cf5a2b8 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -10,7 +10,7 @@ #include <linux/pm_runtime.h> #include <linux/regmap.h> -#include <dt-bindings/clock/qcom,sm8450-videocc.h> +#include <dt-bindings/clock/qcom,sm8650-videocc.h> #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -380,6 +380,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = { [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 }, + [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 }, }; static const struct regmap_config video_cc_sm8550_regmap_config = { |