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author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2024-04-24 04:39:30 +0300 |
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committer | Bjorn Andersson <andersson@kernel.org> | 2024-04-27 13:14:56 -0500 |
commit | 1113501cfb46d5c0eb960f0a8a9f6c0f91dc6fb6 (patch) | |
tree | 4f56ea8dbbc7fe435eb4168c235d05ae387dda12 /drivers/clk/qcom/dispcc-sm8550.c | |
parent | e801038a02ce1e8c652a0b668dd233a4ee48aeb7 (diff) | |
download | lwn-1113501cfb46d5c0eb960f0a8a9f6c0f91dc6fb6.tar.gz lwn-1113501cfb46d5c0eb960f0a8a9f6c0f91dc6fb6.zip |
clk: qcom: dispcc-sm6350: fix DisplayPort clocks
On SM6350 DisplayPort link clocks use frequency tables inherited from
the vendor kernel, it is not applicable in the upstream kernel. Drop
frequency tables and use clk_byte2_ops for those clocks.
This fixes frequency selection in the OPP core (which otherwise attempts
to use invalid 810 KHz as DP link rate), also fixing the following
message:
msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-2-b44038f3fa96@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/dispcc-sm8550.c')
0 files changed, 0 insertions, 0 deletions