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| author | Philippe Schenker <philippe.schenker@toradex.com> | 2023-03-14 11:23:54 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2023-03-27 10:10:21 +0800 |
| commit | 7171ec2953ab34d87d01a8884af3c9e4ba6e515c (patch) | |
| tree | 0f5a9be863cea6c5f827b599c2ebd31dc1d00bc6 /arch | |
| parent | bd74f83de7665dfb5a55db537ed514471b2205b1 (diff) | |
| download | lwn-7171ec2953ab34d87d01a8884af3c9e4ba6e515c.tar.gz lwn-7171ec2953ab34d87d01a8884af3c9e4ba6e515c.zip | |
arm64: dts: colibri-imx8x: Add separate pinctrl group for cs2
Add a separate pinctrl group for chip-select 2 for Colibri SPI. That way
one is able to use it separately.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 26bf14cf5343..1d4e127ffa7e 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -120,7 +120,7 @@ &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>, - <&pinctrl_hog2>; + <&pinctrl_hog2>, <&pinctrl_lpspi2_cs2>; /* On-module touch pen-down interrupt */ pinctrl_ad7879_int: ad7879intgrp { @@ -223,8 +223,7 @@ }; pinctrl_hog0: hog0grp { - fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020>, /* SODIMM 65 */ - <IMX8QXP_CSI_D07_CI_PI_D09 0x61>, /* SODIMM 65 */ + fsl,pins = <IMX8QXP_CSI_D07_CI_PI_D09 0x61>, /* SODIMM 65 */ <IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20>, /* SODIMM 69 */ <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */ <IMX8QXP_CSI_D02_CI_PI_D04 0x61>, /* SODIMM 79 */ @@ -327,6 +326,10 @@ <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040>; /* SODIMM 88 */ }; + pinctrl_lpspi2_cs2: lpspi2cs2grp { + fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x21>; /* SODIMM 65 */ + }; + /* Colibri UART_B */ pinctrl_lpuart0: lpuart0grp { fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020>, /* SODIMM 36 */ |