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| author | Alexandre Ghiti <alexghiti@rivosinc.com> | 2024-11-03 15:51:42 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-11-11 07:33:09 -0800 |
| commit | af042c457db07db4bc1baa5c22d089cab69cfc5b (patch) | |
| tree | 4d792580a0d0155bbd452df8958ca5fb301c91cd /arch/riscv | |
| parent | 010e12aa4925b36700ebacb763a7e6cfd771d9a2 (diff) | |
| download | lwn-af042c457db07db4bc1baa5c22d089cab69cfc5b.tar.gz lwn-af042c457db07db4bc1baa5c22d089cab69cfc5b.zip | |
riscv: Do not fail to build on byte/halfword operations with Zawrs
riscv does not have lr instructions on byte and halfword but the
qspinlock implementation actually uses such atomics provided by the
Zabha extension, so those sizes are legitimate.
Then instead of failing to build, just fallback to the !Zawrs path.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20241103145153.105097-3-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/include/asm/cmpxchg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index ebbce134917c..ac1d7df898ef 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -245,6 +245,11 @@ static __always_inline void __cmpwait(volatile void *ptr, : : : : no_zawrs); switch (size) { + case 1: + fallthrough; + case 2: + /* RISC-V doesn't have lr instructions on byte and half-word. */ + goto no_zawrs; case 4: asm volatile( " lr.w %0, %1\n" |