diff options
| author | Christophe Leroy <christophe.leroy@c-s.fr> | 2019-02-21 10:37:57 +0000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2019-02-22 00:10:16 +1100 |
| commit | 6790dae886f9a95018c52165171b905a8cc47588 (patch) | |
| tree | cb64ea140d7c0ecdbe3546524d3aaeea2310ad5a /arch/powerpc/mm/ppc_mmu_32.c | |
| parent | 2c12393f577396a51b7e0537bd3eb29dcc26dc1b (diff) | |
| download | lwn-6790dae886f9a95018c52165171b905a8cc47588.tar.gz lwn-6790dae886f9a95018c52165171b905a8cc47588.zip | |
powerpc/hash32: use physical address directly in hash handlers.
Since commit c62ce9ef97ba ("powerpc: remove remaining bits from
CONFIG_APUS"), tophys() has become a pure constant operation.
PAGE_OFFSET is known at compile time so the physical address
can be builtin directly.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/mm/ppc_mmu_32.c')
| -rw-r--r-- | arch/powerpc/mm/ppc_mmu_32.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c index 3f4193201ee7..fb747bb0b3e4 100644 --- a/arch/powerpc/mm/ppc_mmu_32.c +++ b/arch/powerpc/mm/ppc_mmu_32.c @@ -231,7 +231,8 @@ void __init MMU_init_hw(void) if (lg_n_hpteg > 16) mb2 = 16 - LG_HPTEG_SIZE; - modify_instruction_site(&patch__hash_page_A0, 0xffff, (unsigned int)Hash >> 16); + modify_instruction_site(&patch__hash_page_A0, 0xffff, + ((unsigned int)Hash - PAGE_OFFSET) >> 16); modify_instruction_site(&patch__hash_page_A1, 0x7c0, mb << 6); modify_instruction_site(&patch__hash_page_A2, 0x7c0, mb2 << 6); modify_instruction_site(&patch__hash_page_B, 0xffff, hmask); @@ -240,7 +241,8 @@ void __init MMU_init_hw(void) /* * Patch up the instructions in hashtable.S:flush_hash_page */ - modify_instruction_site(&patch__flush_hash_A0, 0xffff, (unsigned int)Hash >> 16); + modify_instruction_site(&patch__flush_hash_A0, 0xffff, + ((unsigned int)Hash - PAGE_OFFSET) >> 16); modify_instruction_site(&patch__flush_hash_A1, 0x7c0, mb << 6); modify_instruction_site(&patch__flush_hash_A2, 0x7c0, mb2 << 6); modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask); |