diff options
| author | Sander Vanheule <sander@svanheule.net> | 2023-01-15 13:19:22 +0100 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-01-27 17:13:40 +0100 |
| commit | b74cc639f796ecc0b43b23424ee33d9a56dfa468 (patch) | |
| tree | 006bb44d4d7ecd626cabaa9a9090e04c3b5d5b3b /arch/mips | |
| parent | 4a24f6e0cc17ba259d72c5f687dd8e02098a2b7e (diff) | |
| download | lwn-b74cc639f796ecc0b43b23424ee33d9a56dfa468.tar.gz lwn-b74cc639f796ecc0b43b23424ee33d9a56dfa468.zip | |
mips: Realtek RTL: select NO_EXCEPT_FILL
The CPUs in these SoCs support MIPS32 R2, and allow ebase relocation.
Even if the default exception base of 0x80000000 is used, the
MIPS_GENERIC load address of 0x80100000 leaves sufficient space to not
need an extra 0x400 bytes of padding.
Suggested-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 15cb692b0a09..37072e15b263 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -445,6 +445,7 @@ config LANTIQ select IRQ_MIPS_CPU select CEVT_R4K select CSRC_R4K + select NO_EXCEPT_FILL select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_BIG_ENDIAN |