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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2023-02-27 18:46:13 +0000 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-02-27 23:44:57 +0100 |
| commit | fea8826d5fdc4ff5c93e883a738597129614039c (patch) | |
| tree | a4427ea43c2031f51e2d7a14ad912bfb3399f55a /arch/mips/include | |
| parent | dd8314739a1ff8ed081d3a06f5f87045f7384636 (diff) | |
| download | lwn-fea8826d5fdc4ff5c93e883a738597129614039c.tar.gz lwn-fea8826d5fdc4ff5c93e883a738597129614039c.zip | |
MIPS: smp-cps: Don't rely on CP0_CMGCRBASE
CP0_CMGCRBASE is not always available on CPS enabled system
such as early proAptiv.
For early SMP bring up where we can't safely access memeory,
we patch the entry of CPS NMI vector to inject CMGCR address
directly into register during early core bringup.
For VPE bringup as the core is already coherenct at that point
we just read the variable to obtain the address.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/smp-cps.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h index 7e5b9411faee..22a572b70fe3 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -7,6 +7,8 @@ #ifndef __MIPS_ASM_SMP_CPS_H__ #define __MIPS_ASM_SMP_CPS_H__ +#define CPS_ENTRY_PATCH_INSNS 6 + #ifndef __ASSEMBLY__ struct vpe_boot_config { @@ -30,6 +32,8 @@ extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); extern void mips_cps_pm_save(void); extern void mips_cps_pm_restore(void); +extern void *mips_cps_core_entry_patch_end; + #ifdef CONFIG_MIPS_CPS extern bool mips_cps_smp_in_use(void); |