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| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2023-06-19 06:09:38 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-06-21 14:50:23 +0200 |
| commit | 04b153abdfcbaba70ceef5a846067d4447fd0078 (patch) | |
| tree | 71c27e3218ca868879206fee6648c8a6197c69b2 /arch/mips/include/asm | |
| parent | 7cd1bb48885449a9323c7ff0f10012925e93b4e1 (diff) | |
| download | lwn-04b153abdfcbaba70ceef5a846067d4447fd0078.tar.gz lwn-04b153abdfcbaba70ceef5a846067d4447fd0078.zip | |
mips: ralink: mt7620: remove clock related code
A proper clock driver for ralink SoCs has been added. Hence there is no
need to have clock related code in 'arch/mips/ralink' folder anymore.
Since this is the last clock related code removal, remove also remaining
prototypes in 'common.h' header file.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/mach-ralink/mt7620.h | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h index 3e37705ea9cf..62f4f072c003 100644 --- a/arch/mips/include/asm/mach-ralink/mt7620.h +++ b/arch/mips/include/asm/mach-ralink/mt7620.h @@ -20,52 +20,17 @@ #define SYSC_REG_CHIP_REV 0x0c #define SYSC_REG_SYSTEM_CONFIG0 0x10 #define SYSC_REG_SYSTEM_CONFIG1 0x14 -#define SYSC_REG_CLKCFG0 0x2c -#define SYSC_REG_CPU_SYS_CLKCFG 0x3c -#define SYSC_REG_CPLL_CONFIG0 0x54 -#define SYSC_REG_CPLL_CONFIG1 0x58 #define MT7620_CHIP_NAME0 0x3637544d #define MT7620_CHIP_NAME1 0x20203032 #define MT7628_CHIP_NAME1 0x20203832 -#define SYSCFG0_XTAL_FREQ_SEL BIT(6) - #define CHIP_REV_PKG_MASK 0x1 #define CHIP_REV_PKG_SHIFT 16 #define CHIP_REV_VER_MASK 0xf #define CHIP_REV_VER_SHIFT 8 #define CHIP_REV_ECO_MASK 0xf -#define CLKCFG0_PERI_CLK_SEL BIT(4) - -#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16 -#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf -#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */ -#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */ -#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */ -#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */ -#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */ -#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */ -#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */ -#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */ -#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */ -#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8 -#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f -#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0 -#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f - -#define CPLL_CFG0_SW_CFG BIT(31) -#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16 -#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7 -#define CPLL_CFG0_LC_CURFCK BIT(15) -#define CPLL_CFG0_BYPASS_REF_CLK BIT(14) -#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10 -#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3 - -#define CPLL_CFG1_CPU_AUX1 BIT(25) -#define CPLL_CFG1_CPU_AUX0 BIT(24) - #define SYSCFG0_DRAM_TYPE_MASK 0x3 #define SYSCFG0_DRAM_TYPE_SHIFT 4 #define SYSCFG0_DRAM_TYPE_SDRAM 0 |