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| author | Quentin Schulz <quentin.schulz@bootlin.com> | 2018-07-25 14:26:20 +0200 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2018-07-30 10:34:28 -0700 |
| commit | 6386889ac23e2c1c8276a111765421577539dd7a (patch) | |
| tree | e7c7fe235e3e8b8a4c54d3e505e99189a6b6b830 /arch/mips/boot | |
| parent | 0211d49e5200554eb836c9a12a247d4c11fe571c (diff) | |
| download | lwn-6386889ac23e2c1c8276a111765421577539dd7a.tar.gz lwn-6386889ac23e2c1c8276a111765421577539dd7a.zip | |
MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller
The GPIO controller also serves as an interrupt controller for events
on the GPIO it handles.
An interrupt occurs whenever a GPIO line has changed.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20015/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
Diffstat (limited to 'arch/mips/boot')
| -rw-r--r-- | arch/mips/boot/dts/mscc/ocelot.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi index d7f0e3551500..afe8fc9011ea 100644 --- a/arch/mips/boot/dts/mscc/ocelot.dtsi +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi @@ -168,6 +168,9 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&gpio 0 0 22>; + interrupt-controller; + interrupts = <13>; + #interrupt-cells = <2>; uart_pins: uart-pins { pins = "GPIO_6", "GPIO_7"; |