From 6386889ac23e2c1c8276a111765421577539dd7a Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 25 Jul 2018 14:26:20 +0200 Subject: MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller The GPIO controller also serves as an interrupt controller for events on the GPIO it handles. An interrupt occurs whenever a GPIO line has changed. Signed-off-by: Quentin Schulz Acked-by: Alexandre Belloni Reviewed-by: Linus Walleij Signed-off-by: Paul Burton Patchwork: https://patchwork.linux-mips.org/patch/20015/ Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: linux-gpio@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: thomas.petazzoni@bootlin.com --- arch/mips/boot/dts/mscc/ocelot.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/mips/boot') diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi index d7f0e3551500..afe8fc9011ea 100644 --- a/arch/mips/boot/dts/mscc/ocelot.dtsi +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi @@ -168,6 +168,9 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&gpio 0 0 22>; + interrupt-controller; + interrupts = <13>; + #interrupt-cells = <2>; uart_pins: uart-pins { pins = "GPIO_6", "GPIO_7"; -- cgit v1.2.3