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| author | Kelvin Cheung <keguang.zhang@gmail.com> | 2016-04-06 20:34:54 +0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 14:02:05 +0200 |
| commit | 9ec88b60cb481a6862dc98a78400a6945d9675ba (patch) | |
| tree | 1ab93bc4c34b01530eebae043780ea2469c9f917 /arch/mips/Kconfig | |
| parent | 0d61ed17dd30fc31533ce07750d03bdb34fb6d7a (diff) | |
| download | lwn-9ec88b60cb481a6862dc98a78400a6945d9675ba.tar.gz lwn-9ec88b60cb481a6862dc98a78400a6945d9675ba.zip | |
MIPS: Loongson1B: Some updates/fixes for LS1B
- Add DMA device
- Add NAND device
- Add GPIO device
- Add LED device
- Update the defconfig and rename it to loongson1b_defconfig
- Fix ioremap size
- Other minor fixes
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-clk@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: dmaengine@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-mtd@lists.infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/13033/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 79a1c6991c08..fbd63ff8eba4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1387,6 +1387,8 @@ config CPU_LOONGSON1B bool "Loongson 1B" depends on SYS_HAS_CPU_LOONGSON1B select CPU_LOONGSON1 + select ARCH_WANT_OPTIONAL_GPIOLIB + select LEDS_GPIO_REGISTER help The Loongson 1B is a 32-bit SoC, which implements the MIPS32 release 2 instruction set. |