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| author | Rob Herring (Arm) <robh@kernel.org> | 2024-07-31 10:51:24 -0600 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2024-08-16 13:09:12 +0100 |
| commit | d8226d8cfbaf5eb9771af8ad8b4e58697e2ffb74 (patch) | |
| tree | dd53139085c19105c854dcdd188291e4c6baf1d8 /arch/arm64/tools | |
| parent | 2f62701fa5b0ee94c68d2fcfc470d08aef195441 (diff) | |
| download | lwn-d8226d8cfbaf5eb9771af8ad8b4e58697e2ffb74.tar.gz lwn-d8226d8cfbaf5eb9771af8ad8b4e58697e2ffb74.zip | |
perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter
Armv9.4/8.9 PMU adds optional support for a fixed instruction counter
similar to the fixed cycle counter. Support for the feature is indicated
in the ID_AA64DFR1_EL1 register PMICNTR field. The counter is not
accessible in AArch32.
Existing userspace using direct counter access won't know how to handle
the fixed instruction counter, so we have to avoid using the counter
when user access is requested.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Tested-by: James Clark <james.clark@linaro.org>
Link: https://lore.kernel.org/r/20240731-arm-pmu-3-9-icntr-v3-7-280a8d7ff465@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/tools')
| -rw-r--r-- | arch/arm64/tools/sysreg | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 37aa7eaad07b..8d637ac4b7c6 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2029,6 +2029,31 @@ Sysreg FAR_EL1 3 0 6 0 0 Field 63:0 ADDR EndSysreg +Sysreg PMICNTR_EL0 3 3 9 4 0 +Field 63:0 ICNT +EndSysreg + +Sysreg PMICFILTR_EL0 3 3 9 6 0 +Res0 63:59 +Field 58 SYNC +Field 57:56 VS +Res0 55:32 +Field 31 P +Field 30 U +Field 29 NSK +Field 28 NSU +Field 27 NSH +Field 26 M +Res0 25 +Field 24 SH +Field 23 T +Field 22 RLK +Field 21 RLU +Field 20 RLH +Res0 19:16 +Field 15:0 evtCount +EndSysreg + Sysreg PMSCR_EL1 3 0 9 9 0 Res0 63:8 Field 7:6 PCT |